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authorClifford Wolf <clifford@clifford.at>2014-07-26 11:58:03 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-26 11:58:03 +0200
commitcc4f10883bcc5f0a3c1b4f0937e60be3c6a1b121 (patch)
tree2d417ab32f95d109a0d8438ae7a14acf51783c5b /passes/abc
parent665759fceee4a0db3e776b7912e976eea2ff29a3 (diff)
Renamed RTLIL::{Module,Cell}::connections to connections_
Diffstat (limited to 'passes/abc')
-rw-r--r--passes/abc/abc.cc84
-rw-r--r--passes/abc/blifparse.cc12
2 files changed, 48 insertions, 48 deletions
diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc
index 980e69aa..80828e15 100644
--- a/passes/abc/abc.cc
+++ b/passes/abc/abc.cc
@@ -111,11 +111,11 @@ static void extract_cell(RTLIL::Cell *cell, bool keepff)
{
if (clk_polarity != (cell->type == "$_DFF_P_"))
return;
- if (clk_sig != assign_map(cell->connections["\\C"]))
+ if (clk_sig != assign_map(cell->connections_["\\C"]))
return;
- RTLIL::SigSpec sig_d = cell->connections["\\D"];
- RTLIL::SigSpec sig_q = cell->connections["\\Q"];
+ RTLIL::SigSpec sig_d = cell->connections_["\\D"];
+ RTLIL::SigSpec sig_q = cell->connections_["\\Q"];
if (keepff)
for (auto &c : sig_q.chunks())
@@ -133,8 +133,8 @@ static void extract_cell(RTLIL::Cell *cell, bool keepff)
if (cell->type == "$_INV_")
{
- RTLIL::SigSpec sig_a = cell->connections["\\A"];
- RTLIL::SigSpec sig_y = cell->connections["\\Y"];
+ RTLIL::SigSpec sig_a = cell->connections_["\\A"];
+ RTLIL::SigSpec sig_y = cell->connections_["\\Y"];
assign_map.apply(sig_a);
assign_map.apply(sig_y);
@@ -147,9 +147,9 @@ static void extract_cell(RTLIL::Cell *cell, bool keepff)
if (cell->type == "$_AND_" || cell->type == "$_OR_" || cell->type == "$_XOR_")
{
- RTLIL::SigSpec sig_a = cell->connections["\\A"];
- RTLIL::SigSpec sig_b = cell->connections["\\B"];
- RTLIL::SigSpec sig_y = cell->connections["\\Y"];
+ RTLIL::SigSpec sig_a = cell->connections_["\\A"];
+ RTLIL::SigSpec sig_b = cell->connections_["\\B"];
+ RTLIL::SigSpec sig_y = cell->connections_["\\Y"];
assign_map.apply(sig_a);
assign_map.apply(sig_b);
@@ -173,10 +173,10 @@ static void extract_cell(RTLIL::Cell *cell, bool keepff)
if (cell->type == "$_MUX_")
{
- RTLIL::SigSpec sig_a = cell->connections["\\A"];
- RTLIL::SigSpec sig_b = cell->connections["\\B"];
- RTLIL::SigSpec sig_s = cell->connections["\\S"];
- RTLIL::SigSpec sig_y = cell->connections["\\Y"];
+ RTLIL::SigSpec sig_a = cell->connections_["\\A"];
+ RTLIL::SigSpec sig_b = cell->connections_["\\B"];
+ RTLIL::SigSpec sig_s = cell->connections_["\\S"];
+ RTLIL::SigSpec sig_y = cell->connections_["\\Y"];
assign_map.apply(sig_a);
assign_map.apply(sig_b);
@@ -347,7 +347,7 @@ static void handle_loops()
}
edges[id1].swap(edges[id3]);
- module->connections.push_back(RTLIL::SigSig(signal_list[id3].bit, signal_list[id1].bit));
+ module->connections_.push_back(RTLIL::SigSig(signal_list[id3].bit, signal_list[id1].bit));
dump_loop_graph(dot_f, dot_nr, edges, workpool, in_edges_count);
}
}
@@ -470,7 +470,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
if (cell->type != "$_DFF_N_" && cell->type != "$_DFF_P_")
continue;
- std::pair<bool, RTLIL::SigSpec> key(cell->type == "$_DFF_P_", assign_map(cell->connections.at("\\C")));
+ std::pair<bool, RTLIL::SigSpec> key(cell->type == "$_DFF_P_", assign_map(cell->connections_.at("\\C")));
if (++dff_counters[key] > best_dff_counter) {
best_dff_counter = dff_counters[key];
clk_polarity = key.first;
@@ -503,7 +503,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
}
for (auto &cell_it : module->cells)
- for (auto &port_it : cell_it.second->connections)
+ for (auto &port_it : cell_it.second->connections_)
mark_port(port_it.second);
handle_loops();
@@ -705,48 +705,48 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
cell_stats[RTLIL::unescape_id(c->type)]++;
if (c->type == "\\ZERO" || c->type == "\\ONE") {
RTLIL::SigSig conn;
- conn.first = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].as_wire()->name)]);
+ conn.first = RTLIL::SigSpec(module->wires[remap_name(c->connections_["\\Y"].as_wire()->name)]);
conn.second = RTLIL::SigSpec(c->type == "\\ZERO" ? 0 : 1, 1);
- module->connections.push_back(conn);
+ module->connections_.push_back(conn);
continue;
}
if (c->type == "\\BUF") {
RTLIL::SigSig conn;
- conn.first = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].as_wire()->name)]);
- conn.second = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\A"].as_wire()->name)]);
- module->connections.push_back(conn);
+ conn.first = RTLIL::SigSpec(module->wires[remap_name(c->connections_["\\Y"].as_wire()->name)]);
+ conn.second = RTLIL::SigSpec(module->wires[remap_name(c->connections_["\\A"].as_wire()->name)]);
+ module->connections_.push_back(conn);
continue;
}
if (c->type == "\\INV") {
RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_INV_");
- cell->connections["\\A"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\A"].as_wire()->name)]);
- cell->connections["\\Y"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].as_wire()->name)]);
+ cell->connections_["\\A"] = RTLIL::SigSpec(module->wires[remap_name(c->connections_["\\A"].as_wire()->name)]);
+ cell->connections_["\\Y"] = RTLIL::SigSpec(module->wires[remap_name(c->connections_["\\Y"].as_wire()->name)]);
design->select(module, cell);
continue;
}
if (c->type == "\\AND" || c->type == "\\OR" || c->type == "\\XOR") {
RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_" + c->type.substr(1) + "_");
- cell->connections["\\A"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\A"].as_wire()->name)]);
- cell->connections["\\B"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\B"].as_wire()->name)]);
- cell->connections["\\Y"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].as_wire()->name)]);
+ cell->connections_["\\A"] = RTLIL::SigSpec(module->wires[remap_name(c->connections_["\\A"].as_wire()->name)]);
+ cell->connections_["\\B"] = RTLIL::SigSpec(module->wires[remap_name(c->connections_["\\B"].as_wire()->name)]);
+ cell->connections_["\\Y"] = RTLIL::SigSpec(module->wires[remap_name(c->connections_["\\Y"].as_wire()->name)]);
design->select(module, cell);
continue;
}
if (c->type == "\\MUX") {
RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_MUX_");
- cell->connections["\\A"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\A"].as_wire()->name)]);
- cell->connections["\\B"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\B"].as_wire()->name)]);
- cell->connections["\\S"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\S"].as_wire()->name)]);
- cell->connections["\\Y"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].as_wire()->name)]);
+ cell->connections_["\\A"] = RTLIL::SigSpec(module->wires[remap_name(c->connections_["\\A"].as_wire()->name)]);
+ cell->connections_["\\B"] = RTLIL::SigSpec(module->wires[remap_name(c->connections_["\\B"].as_wire()->name)]);
+ cell->connections_["\\S"] = RTLIL::SigSpec(module->wires[remap_name(c->connections_["\\S"].as_wire()->name)]);
+ cell->connections_["\\Y"] = RTLIL::SigSpec(module->wires[remap_name(c->connections_["\\Y"].as_wire()->name)]);
design->select(module, cell);
continue;
}
if (c->type == "\\DFF") {
log_assert(clk_sig.size() == 1);
RTLIL::Cell *cell = module->addCell(remap_name(c->name), clk_polarity ? "$_DFF_P_" : "$_DFF_N_");
- cell->connections["\\D"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\D"].as_wire()->name)]);
- cell->connections["\\Q"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Q"].as_wire()->name)]);
- cell->connections["\\C"] = clk_sig;
+ cell->connections_["\\D"] = RTLIL::SigSpec(module->wires[remap_name(c->connections_["\\D"].as_wire()->name)]);
+ cell->connections_["\\Q"] = RTLIL::SigSpec(module->wires[remap_name(c->connections_["\\Q"].as_wire()->name)]);
+ cell->connections_["\\C"] = clk_sig;
design->select(module, cell);
continue;
}
@@ -761,23 +761,23 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
cell_stats[RTLIL::unescape_id(c->type)]++;
if (c->type == "\\_const0_" || c->type == "\\_const1_") {
RTLIL::SigSig conn;
- conn.first = RTLIL::SigSpec(module->wires[remap_name(c->connections.begin()->second.as_wire()->name)]);
+ conn.first = RTLIL::SigSpec(module->wires[remap_name(c->connections_.begin()->second.as_wire()->name)]);
conn.second = RTLIL::SigSpec(c->type == "\\_const0_" ? 0 : 1, 1);
- module->connections.push_back(conn);
+ module->connections_.push_back(conn);
continue;
}
if (c->type == "\\_dff_") {
log_assert(clk_sig.size() == 1);
RTLIL::Cell *cell = module->addCell(remap_name(c->name), clk_polarity ? "$_DFF_P_" : "$_DFF_N_");
- cell->connections["\\D"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\D"].as_wire()->name)]);
- cell->connections["\\Q"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Q"].as_wire()->name)]);
- cell->connections["\\C"] = clk_sig;
+ cell->connections_["\\D"] = RTLIL::SigSpec(module->wires[remap_name(c->connections_["\\D"].as_wire()->name)]);
+ cell->connections_["\\Q"] = RTLIL::SigSpec(module->wires[remap_name(c->connections_["\\Q"].as_wire()->name)]);
+ cell->connections_["\\C"] = clk_sig;
design->select(module, cell);
continue;
}
RTLIL::Cell *cell = module->addCell(remap_name(c->name), c->type);
cell->parameters = c->parameters;
- for (auto &conn : c->connections) {
+ for (auto &conn : c->connections_) {
RTLIL::SigSpec newsig;
for (auto &c : conn.second.chunks()) {
if (c.width == 0)
@@ -785,18 +785,18 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
assert(c.width == 1);
newsig.append(module->wires[remap_name(c.wire->name)]);
}
- cell->connections[conn.first] = newsig;
+ cell->connections_[conn.first] = newsig;
}
design->select(module, cell);
}
}
- for (auto conn : mapped_mod->connections) {
+ for (auto conn : mapped_mod->connections_) {
if (!conn.first.is_fully_const())
conn.first = RTLIL::SigSpec(module->wires[remap_name(conn.first.as_wire()->name)]);
if (!conn.second.is_fully_const())
conn.second = RTLIL::SigSpec(module->wires[remap_name(conn.second.as_wire()->name)]);
- module->connections.push_back(conn);
+ module->connections_.push_back(conn);
}
for (auto &it : cell_stats)
@@ -816,7 +816,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
conn.second = si.bit;
in_wires++;
}
- module->connections.push_back(conn);
+ module->connections_.push_back(conn);
}
log("ABC RESULTS: internal signals: %8d\n", int(signal_list.size()) - in_wires - out_wires);
log("ABC RESULTS: input signals: %8d\n", in_wires);
diff --git a/passes/abc/blifparse.cc b/passes/abc/blifparse.cc
index e7feb187..122f7845 100644
--- a/passes/abc/blifparse.cc
+++ b/passes/abc/blifparse.cc
@@ -128,8 +128,8 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name)
}
RTLIL::Cell *cell = module->addCell(NEW_ID, dff_name);
- cell->connections["\\D"] = module->wires.at(RTLIL::escape_id(d));
- cell->connections["\\Q"] = module->wires.at(RTLIL::escape_id(q));
+ cell->connections_["\\D"] = module->wires.at(RTLIL::escape_id(d));
+ cell->connections_["\\Q"] = module->wires.at(RTLIL::escape_id(q));
continue;
}
@@ -148,7 +148,7 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name)
*(q++) = 0;
if (module->wires.count(RTLIL::escape_id(q)) == 0)
module->addWire(RTLIL::escape_id(q));
- cell->connections[RTLIL::escape_id(p)] = module->wires.at(RTLIL::escape_id(q));
+ cell->connections_[RTLIL::escape_id(p)] = module->wires.at(RTLIL::escape_id(q));
}
continue;
}
@@ -199,15 +199,15 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name)
finished_parsing_constval:
if (state == RTLIL::State::Sa)
state = RTLIL::State::S1;
- module->connections.push_back(RTLIL::SigSig(output_sig, state));
+ module->connections_.push_back(RTLIL::SigSig(output_sig, state));
goto continue_without_read;
}
RTLIL::Cell *cell = module->addCell(NEW_ID, "$lut");
cell->parameters["\\WIDTH"] = RTLIL::Const(input_sig.size());
cell->parameters["\\LUT"] = RTLIL::Const(RTLIL::State::Sx, 1 << input_sig.size());
- cell->connections["\\I"] = input_sig;
- cell->connections["\\O"] = output_sig;
+ cell->connections_["\\I"] = input_sig;
+ cell->connections_["\\O"] = output_sig;
lutptr = &cell->parameters.at("\\LUT");
lut_default_state = RTLIL::State::Sx;
continue;