diff options
| author | Clifford Wolf <clifford@clifford.at> | 2014-07-23 09:48:26 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-23 09:52:55 +0200 |
| commit | ec923652e2eb721aa16657e54a67666f855c3d65 (patch) | |
| tree | 934ce8ee55c3c58a1e2c11f19eec194665413906 /passes/abc | |
| parent | a8d3a68971ccc4e47c54a906aae374a9a54b1415 (diff) | |
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3
Diffstat (limited to 'passes/abc')
| -rw-r--r-- | passes/abc/abc.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc index fa2c4960..8cdd39b7 100644 --- a/passes/abc/abc.cc +++ b/passes/abc/abc.cc @@ -466,7 +466,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std clk_str = clk_str.substr(1); } if (module->wires.count(RTLIL::escape_id(clk_str)) != 0) - clk_sig = assign_map(RTLIL::SigSpec::grml(module->wires.at(RTLIL::escape_id(clk_str)), 0)); + clk_sig = assign_map(RTLIL::SigSpec(module->wires.at(RTLIL::escape_id(clk_str)), 0)); } if (dff_mode && clk_sig.size() == 0) |