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authorClifford Wolf <clifford@clifford.at>2014-08-15 14:11:40 +0200
committerClifford Wolf <clifford@clifford.at>2014-08-15 14:11:40 +0200
commitf092b5014895dc5dc62b8103fcedf94cfa9f85a8 (patch)
tree2f09add560746030249fe333e551de2f113bccdb /passes/abc
parentbf486002d9a6d976b3d086700ccdcfb0fb70ba0b (diff)
Renamed $_INV_ cell type to $_NOT_
Diffstat (limited to 'passes/abc')
-rw-r--r--passes/abc/abc.cc4
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc
index e7da6ed4..2b1d4981 100644
--- a/passes/abc/abc.cc
+++ b/passes/abc/abc.cc
@@ -130,7 +130,7 @@ static void extract_cell(RTLIL::Cell *cell, bool keepff)
return;
}
- if (cell->type == "$_INV_")
+ if (cell->type == "$_NOT_")
{
RTLIL::SigSpec sig_a = cell->getPort("\\A");
RTLIL::SigSpec sig_y = cell->getPort("\\Y");
@@ -733,7 +733,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
continue;
}
if (c->type == "\\INV") {
- RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_INV_");
+ RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_NOT_");
cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]));
cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]));
design->select(module, cell);