diff options
| author | Clifford Wolf <clifford@clifford.at> | 2014-07-27 10:18:00 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-27 11:18:30 +0200 |
| commit | 10e5791c5e5660cb784503d36439ee90d61eb06b (patch) | |
| tree | d7bd3d8f1d0254e14fcf68ce25545f42afab9724 /passes/cmds/add.cc | |
| parent | d088854b47f5f77c6a62be2ba4b895164938d7a2 (diff) | |
Refactoring: Renamed RTLIL::Design::modules to modules_
Diffstat (limited to 'passes/cmds/add.cc')
| -rw-r--r-- | passes/cmds/add.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/passes/cmds/add.cc b/passes/cmds/add.cc index 49aa7c98..62995a49 100644 --- a/passes/cmds/add.cc +++ b/passes/cmds/add.cc @@ -64,10 +64,10 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n for (auto &it : module->cells_) { - if (design->modules.count(it.second->type) == 0) + if (design->modules_.count(it.second->type) == 0) continue; - RTLIL::Module *mod = design->modules.at(it.second->type); + RTLIL::Module *mod = design->modules_.at(it.second->type); if (!design->selected_whole_module(mod->name)) continue; if (mod->get_bool_attribute("\\blackbox")) @@ -136,7 +136,7 @@ struct AddPass : public Pass { } extra_args(args, argidx, design); - for (auto &mod : design->modules) + for (auto &mod : design->modules_) { RTLIL::Module *module = mod.second; if (!design->selected_whole_module(module->name)) |