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authorClifford Wolf <clifford@clifford.at>2014-07-26 20:12:50 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-26 20:12:50 +0200
commit946ddff9cef3ea0b4dad8664319fb13074133775 (patch)
treee35f5ebe3cd76a8e10fe945872e32c2ed3a7d815 /passes/cmds/add.cc
parentd49dec1f861ce11a87c48cc21c8edc1755802a5f (diff)
Changed a lot of code to the new RTLIL::Wire constructors
Diffstat (limited to 'passes/cmds/add.cc')
-rw-r--r--passes/cmds/add.cc5
1 files changed, 1 insertions, 4 deletions
diff --git a/passes/cmds/add.cc b/passes/cmds/add.cc
index f94ea639..7e9ba97e 100644
--- a/passes/cmds/add.cc
+++ b/passes/cmds/add.cc
@@ -47,12 +47,9 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n
}
else
{
- wire = new RTLIL::Wire;
- wire->name = name;
- wire->width = width;
+ wire = module->addWire(name, width);
wire->port_input = flag_input;
wire->port_output = flag_output;
- module->add(wire);
if (flag_input || flag_output) {
wire->port_id = module->wires.size();