diff options
| author | Clifford Wolf <clifford@clifford.at> | 2014-07-26 16:11:28 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-26 16:11:28 +0200 |
| commit | 97a59851a6c411ccb06162d4b31725bf89262378 (patch) | |
| tree | 74cba570ab858657b6fa524cdc9fa45b0493c4be /passes/cmds/add.cc | |
| parent | a84cb0493566f8f5eb610c6d7b67dda85b0f227b (diff) | |
Added RTLIL::Cell::has(portname)
Diffstat (limited to 'passes/cmds/add.cc')
| -rw-r--r-- | passes/cmds/add.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/cmds/add.cc b/passes/cmds/add.cc index 1401193f..f94ea639 100644 --- a/passes/cmds/add.cc +++ b/passes/cmds/add.cc @@ -75,7 +75,7 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n continue; if (mod->get_bool_attribute("\\blackbox")) continue; - if (it.second->connections().count(name) > 0) + if (it.second->has(name)) continue; it.second->set(name, wire); |