diff options
| author | Clifford Wolf <clifford@clifford.at> | 2014-07-26 11:58:03 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-26 11:58:03 +0200 |
| commit | cc4f10883bcc5f0a3c1b4f0937e60be3c6a1b121 (patch) | |
| tree | 2d417ab32f95d109a0d8438ae7a14acf51783c5b /passes/cmds/add.cc | |
| parent | 665759fceee4a0db3e776b7912e976eea2ff29a3 (diff) | |
Renamed RTLIL::{Module,Cell}::connections to connections_
Diffstat (limited to 'passes/cmds/add.cc')
| -rw-r--r-- | passes/cmds/add.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/cmds/add.cc b/passes/cmds/add.cc index acee4c46..ce8ecc32 100644 --- a/passes/cmds/add.cc +++ b/passes/cmds/add.cc @@ -75,10 +75,10 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n continue; if (mod->get_bool_attribute("\\blackbox")) continue; - if (it.second->connections.count(name) > 0) + if (it.second->connections_.count(name) > 0) continue; - it.second->connections[name] = wire; + it.second->connections_[name] = wire; log("Added connection %s to cell %s.%s (%s).\n", name.c_str(), module->name.c_str(), it.first.c_str(), it.second->type.c_str()); } } |