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authorClifford Wolf <clifford@clifford.at>2014-07-26 11:58:03 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-26 11:58:03 +0200
commitcc4f10883bcc5f0a3c1b4f0937e60be3c6a1b121 (patch)
tree2d417ab32f95d109a0d8438ae7a14acf51783c5b /passes/cmds/connwrappers.cc
parent665759fceee4a0db3e776b7912e976eea2ff29a3 (diff)
Renamed RTLIL::{Module,Cell}::connections to connections_
Diffstat (limited to 'passes/cmds/connwrappers.cc')
-rw-r--r--passes/cmds/connwrappers.cc4
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/cmds/connwrappers.cc b/passes/cmds/connwrappers.cc
index 6cb2a892..87ed3d85 100644
--- a/passes/cmds/connwrappers.cc
+++ b/passes/cmds/connwrappers.cc
@@ -74,7 +74,7 @@ struct ConnwrappersWorker
if (!decl_celltypes.count(cell->type))
continue;
- for (auto &conn : cell->connections)
+ for (auto &conn : cell->connections_)
{
std::pair<std::string, std::string> key(cell->type, conn.first);
@@ -109,7 +109,7 @@ struct ConnwrappersWorker
if (!design->selected(module, cell))
continue;
- for (auto &conn : cell->connections)
+ for (auto &conn : cell->connections_)
{
std::vector<RTLIL::SigBit> sigbits = sigmap(conn.second).to_sigbit_vector();
RTLIL::SigSpec old_sig;