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authorClifford Wolf <clifford@clifford.at>2014-08-02 00:45:25 +0200
committerClifford Wolf <clifford@clifford.at>2014-08-02 00:45:25 +0200
commit14412e6c957a34381c33740426b35f7b90a446be (patch)
treed45765adc9aa28301ab0c9d100728a5d720503fd /passes/cmds/delete.cc
parent75ffd1643c97321255bc591edf0c1a7097b8dce9 (diff)
Preparations for RTLIL::IdString redesign: cleanup of existing code
Diffstat (limited to 'passes/cmds/delete.cc')
-rw-r--r--passes/cmds/delete.cc6
1 files changed, 3 insertions, 3 deletions
diff --git a/passes/cmds/delete.cc b/passes/cmds/delete.cc
index 67b4d939..2a91bc9e 100644
--- a/passes/cmds/delete.cc
+++ b/passes/cmds/delete.cc
@@ -64,7 +64,7 @@ struct DeletePass : public Pass {
}
extra_args(args, argidx, design);
- std::vector<std::string> delete_mods;
+ std::vector<RTLIL::IdString> delete_mods;
for (auto &mod_it : design->modules_)
{
@@ -92,8 +92,8 @@ struct DeletePass : public Pass {
std::set<RTLIL::Wire*> delete_wires;
std::set<RTLIL::Cell*> delete_cells;
- std::set<std::string> delete_procs;
- std::set<std::string> delete_mems;
+ std::set<RTLIL::IdString> delete_procs;
+ std::set<RTLIL::IdString> delete_mems;
for (auto &it : module->wires_)
if (design->selected(module, it.second))