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authorClifford Wolf <clifford@clifford.at>2014-02-09 10:03:26 +0100
committerClifford Wolf <clifford@clifford.at>2014-02-09 10:03:26 +0100
commitb6f33576d598b4d9359e1638f4e6ce85b537dbfb (patch)
tree5f49322c7a02e5e70c96bc632dac89a1d972c811 /passes/cmds/delete.cc
parentb3b5fac191999627b61a8f3a0e13d1ce5d97c598 (diff)
Added delete {-input|-output|-port}
Diffstat (limited to 'passes/cmds/delete.cc')
-rw-r--r--passes/cmds/delete.cc41
1 files changed, 36 insertions, 5 deletions
diff --git a/passes/cmds/delete.cc b/passes/cmds/delete.cc
index d75386a9..1c02752c 100644
--- a/passes/cmds/delete.cc
+++ b/passes/cmds/delete.cc
@@ -47,16 +47,34 @@ struct DeletePass : public Pass {
log("Deletes the selected objects. This will also remove entire modules, if the\n");
log("whole module is selected.\n");
log("\n");
+ log("\n");
+ log(" delete {-input|-output|-port} [selection]\n");
+ log("\n");
+ log("Does not delete any object but removes the input and/or output flag on the\n");
+ log("selected wires, thus 'deleting' module ports.\n");
+ log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
+ bool flag_input = false;
+ bool flag_output = false;
+
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
{
- // if (arg[argidx] == "-something") {
- // flag_something = true;
- // continue;
- // }
+ if (args[argidx] == "-input") {
+ flag_input = true;
+ continue;
+ }
+ if (args[argidx] == "-output") {
+ flag_output = true;
+ continue;
+ }
+ if (args[argidx] == "-port") {
+ flag_input = true;
+ flag_output = true;
+ continue;
+ }
break;
}
extra_args(args, argidx, design);
@@ -65,7 +83,7 @@ struct DeletePass : public Pass {
for (auto &mod_it : design->modules)
{
- if (design->selected_whole_module(mod_it.first)) {
+ if (design->selected_whole_module(mod_it.first) && !flag_input && !flag_output) {
delete_mods.push_back(mod_it.first);
continue;
}
@@ -74,6 +92,19 @@ struct DeletePass : public Pass {
continue;
RTLIL::Module *module = mod_it.second;
+
+ if (flag_input || flag_output) {
+ for (auto &it : module->wires)
+ if (design->selected(module, it.second)) {
+ if (flag_input)
+ it.second->port_input = false;
+ if (flag_output)
+ it.second->port_output = false;
+ }
+ module->fixup_ports();
+ continue;
+ }
+
std::set<std::string> delete_wires;
std::set<std::string> delete_cells;
std::set<std::string> delete_procs;