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authorClifford Wolf <clifford@clifford.at>2014-07-27 10:18:00 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-27 11:18:30 +0200
commit10e5791c5e5660cb784503d36439ee90d61eb06b (patch)
treed7bd3d8f1d0254e14fcf68ce25545f42afab9724 /passes/cmds/rename.cc
parentd088854b47f5f77c6a62be2ba4b895164938d7a2 (diff)
Refactoring: Renamed RTLIL::Design::modules to modules_
Diffstat (limited to 'passes/cmds/rename.cc')
-rw-r--r--passes/cmds/rename.cc14
1 files changed, 7 insertions, 7 deletions
diff --git a/passes/cmds/rename.cc b/passes/cmds/rename.cc
index c8b8160f..3a600872 100644
--- a/passes/cmds/rename.cc
+++ b/passes/cmds/rename.cc
@@ -96,7 +96,7 @@ struct RenamePass : public Pass {
{
extra_args(args, argidx, design);
- for (auto &mod : design->modules)
+ for (auto &mod : design->modules_)
{
int counter = 0;
@@ -128,7 +128,7 @@ struct RenamePass : public Pass {
{
extra_args(args, argidx, design);
- for (auto &mod : design->modules)
+ for (auto &mod : design->modules_)
{
RTLIL::Module *module = mod.second;
if (!design->selected(module))
@@ -163,19 +163,19 @@ struct RenamePass : public Pass {
if (!design->selected_active_module.empty())
{
- if (design->modules.count(design->selected_active_module) > 0)
- rename_in_module(design->modules.at(design->selected_active_module), from_name, to_name);
+ if (design->modules_.count(design->selected_active_module) > 0)
+ rename_in_module(design->modules_.at(design->selected_active_module), from_name, to_name);
}
else
{
- for (auto &mod : design->modules) {
+ for (auto &mod : design->modules_) {
if (mod.first == from_name || RTLIL::unescape_id(mod.first) == from_name) {
to_name = RTLIL::escape_id(to_name);
log("Renaming module %s to %s.\n", mod.first.c_str(), to_name.c_str());
RTLIL::Module *module = mod.second;
- design->modules.erase(module->name);
+ design->modules_.erase(module->name);
module->name = to_name;
- design->modules[module->name] = module;
+ design->modules_[module->name] = module;
goto rename_ok;
}
}