diff options
| author | Clifford Wolf <clifford@clifford.at> | 2014-12-26 10:53:21 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-12-26 10:53:21 +0100 |
| commit | a6c96b986be313368b4fa03eba5cf6987448100c (patch) | |
| tree | edb56a97a9c64376e1ee920133c46aeefe539ef1 /passes/cmds/rename.cc | |
| parent | e8c12e5f0c49cca4dd54da12003bd010a488aee3 (diff) | |
Added Yosys::{dict,nodict,vector} container types
Diffstat (limited to 'passes/cmds/rename.cc')
| -rw-r--r-- | passes/cmds/rename.cc | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/passes/cmds/rename.cc b/passes/cmds/rename.cc index b2e10e55..8f24af27 100644 --- a/passes/cmds/rename.cc +++ b/passes/cmds/rename.cc @@ -118,7 +118,7 @@ struct RenamePass : public Pass { if (!design->selected(module)) continue; - std::map<RTLIL::IdString, RTLIL::Wire*> new_wires; + dict<RTLIL::IdString, RTLIL::Wire*> new_wires; for (auto &it : module->wires_) { if (it.first[0] == '$' && design->selected(module, it.second)) do it.second->name = stringf("\\%s%d%s", pattern_prefix.c_str(), counter++, pattern_suffix.c_str()); @@ -128,7 +128,7 @@ struct RenamePass : public Pass { module->wires_.swap(new_wires); module->fixup_ports(); - std::map<RTLIL::IdString, RTLIL::Cell*> new_cells; + dict<RTLIL::IdString, RTLIL::Cell*> new_cells; for (auto &it : module->cells_) { if (it.first[0] == '$' && design->selected(module, it.second)) do it.second->name = stringf("\\%s%d%s", pattern_prefix.c_str(), counter++, pattern_suffix.c_str()); @@ -149,7 +149,7 @@ struct RenamePass : public Pass { if (!design->selected(module)) continue; - std::map<RTLIL::IdString, RTLIL::Wire*> new_wires; + dict<RTLIL::IdString, RTLIL::Wire*> new_wires; for (auto &it : module->wires_) { if (design->selected(module, it.second)) if (it.first[0] == '\\' && it.second->port_id == 0) @@ -159,7 +159,7 @@ struct RenamePass : public Pass { module->wires_.swap(new_wires); module->fixup_ports(); - std::map<RTLIL::IdString, RTLIL::Cell*> new_cells; + dict<RTLIL::IdString, RTLIL::Cell*> new_cells; for (auto &it : module->cells_) { if (design->selected(module, it.second)) if (it.first[0] == '\\') |