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authorClifford Wolf <clifford@clifford.at>2014-11-08 12:38:48 +0100
committerClifford Wolf <clifford@clifford.at>2014-11-08 12:38:48 +0100
commitd92fb5b35eff8c616f1b5de355d13b642e830c8f (patch)
treec5fc276aeec04b43aac15d670b1df2b1fb9e6ed0 /passes/cmds/rename.cc
parent003336c58dcc9bc96484d6e7a9f3033309a747df (diff)
Added missing fixup_ports() calls to "rename" command
Diffstat (limited to 'passes/cmds/rename.cc')
-rw-r--r--passes/cmds/rename.cc4
1 files changed, 4 insertions, 0 deletions
diff --git a/passes/cmds/rename.cc b/passes/cmds/rename.cc
index 1006686e..b2e10e55 100644
--- a/passes/cmds/rename.cc
+++ b/passes/cmds/rename.cc
@@ -36,6 +36,8 @@ static void rename_in_module(RTLIL::Module *module, std::string from_name, std::
if (it.first == from_name) {
log("Renaming wire %s to %s in module %s.\n", log_id(it.second), log_id(to_name), log_id(module));
module->rename(it.second, to_name);
+ if (it.second->port_id)
+ module->fixup_ports();
return;
}
@@ -124,6 +126,7 @@ struct RenamePass : public Pass {
new_wires[it.second->name] = it.second;
}
module->wires_.swap(new_wires);
+ module->fixup_ports();
std::map<RTLIL::IdString, RTLIL::Cell*> new_cells;
for (auto &it : module->cells_) {
@@ -154,6 +157,7 @@ struct RenamePass : public Pass {
new_wires[it.second->name] = it.second;
}
module->wires_.swap(new_wires);
+ module->fixup_ports();
std::map<RTLIL::IdString, RTLIL::Cell*> new_cells;
for (auto &it : module->cells_) {