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authorClifford Wolf <clifford@clifford.at>2015-02-09 00:18:36 +0100
committerClifford Wolf <clifford@clifford.at>2015-02-09 00:18:36 +0100
commitf889e3d38524bb3cb6a10ccd33f788e987c6e14e (patch)
treec7247e4f760c0a7545a22779195b627f3e871506 /passes/cmds/rename.cc
parent139648554dbdfbd9cdeab6736f88914a122fb70a (diff)
Fixed iterator invalidation bug in "rename" command
Diffstat (limited to 'passes/cmds/rename.cc')
-rw-r--r--passes/cmds/rename.cc7
1 files changed, 4 insertions, 3 deletions
diff --git a/passes/cmds/rename.cc b/passes/cmds/rename.cc
index 8f24af27..17d803e9 100644
--- a/passes/cmds/rename.cc
+++ b/passes/cmds/rename.cc
@@ -34,9 +34,10 @@ static void rename_in_module(RTLIL::Module *module, std::string from_name, std::
for (auto &it : module->wires_)
if (it.first == from_name) {
- log("Renaming wire %s to %s in module %s.\n", log_id(it.second), log_id(to_name), log_id(module));
- module->rename(it.second, to_name);
- if (it.second->port_id)
+ Wire *w = it.second;
+ log("Renaming wire %s to %s in module %s.\n", log_id(w), log_id(to_name), log_id(module));
+ module->rename(w, to_name);
+ if (w->port_id)
module->fixup_ports();
return;
}