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authorClifford Wolf <clifford@clifford.at>2014-07-22 20:15:14 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-22 20:39:37 +0200
commit4b4048bc5feba1ab05c7a63f12c0a17879cb7e04 (patch)
tree27801c4b0171a2491ff6817ebb6d2a1d1484c086 /passes/cmds/select.cc
parent16e5ae0b92ac4b7568cb11a769e612e152c0042e (diff)
SigSpec refactoring: using the accessor functions everywhere
Diffstat (limited to 'passes/cmds/select.cc')
-rw-r--r--passes/cmds/select.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc
index 068162eb..123483a3 100644
--- a/passes/cmds/select.cc
+++ b/passes/cmds/select.cc
@@ -415,7 +415,7 @@ static int select_op_expand(RTLIL::Design *design, RTLIL::Selection &lhs, std::v
include_match:
is_input = mode == 'x' || ct.cell_input(cell.second->type, conn.first);
is_output = mode == 'x' || ct.cell_output(cell.second->type, conn.first);
- for (auto &chunk : conn.second.__chunks)
+ for (auto &chunk : conn.second.chunks())
if (chunk.wire != NULL) {
if (max_objects != 0 && selected_wires.count(chunk.wire) > 0 && lhs.selected_members[mod->name].count(cell.first) == 0)
if (mode == 'x' || (mode == 'i' && is_output) || (mode == 'o' && is_input))