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authorClifford Wolf <clifford@clifford.at>2014-07-26 11:58:03 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-26 11:58:03 +0200
commitcc4f10883bcc5f0a3c1b4f0937e60be3c6a1b121 (patch)
tree2d417ab32f95d109a0d8438ae7a14acf51783c5b /passes/cmds/select.cc
parent665759fceee4a0db3e776b7912e976eea2ff29a3 (diff)
Renamed RTLIL::{Module,Cell}::connections to connections_
Diffstat (limited to 'passes/cmds/select.cc')
-rw-r--r--passes/cmds/select.cc4
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc
index 123483a3..5d991d03 100644
--- a/passes/cmds/select.cc
+++ b/passes/cmds/select.cc
@@ -380,7 +380,7 @@ static int select_op_expand(RTLIL::Design *design, RTLIL::Selection &lhs, std::v
if (lhs.selected_member(mod_it.first, it.first) && limits.count(it.first) == 0)
selected_wires.insert(it.second);
- for (auto &conn : mod->connections)
+ for (auto &conn : mod->connections_)
{
std::vector<RTLIL::SigBit> conn_lhs = conn.first.to_sigbit_vector();
std::vector<RTLIL::SigBit> conn_rhs = conn.second.to_sigbit_vector();
@@ -396,7 +396,7 @@ static int select_op_expand(RTLIL::Design *design, RTLIL::Selection &lhs, std::v
}
for (auto &cell : mod->cells)
- for (auto &conn : cell.second->connections)
+ for (auto &conn : cell.second->connections_)
{
char last_mode = '-';
for (auto &rule : rules) {