diff options
| author | Clifford Wolf <clifford@clifford.at> | 2014-07-27 01:51:45 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-27 01:51:45 +0200 |
| commit | 4c4b6021562c598c4510831bd547edaa97d14dac (patch) | |
| tree | 7d8bde9d617e67431bdb6c51b5e27ea1836fe7a5 /passes/cmds/show.cc | |
| parent | f9946232adf887e5aa4a48c64f88eaa17e424009 (diff) | |
Refactoring: Renamed RTLIL::Module::cells to cells_
Diffstat (limited to 'passes/cmds/show.cc')
| -rw-r--r-- | passes/cmds/show.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc index 1feb90af..18af8dfc 100644 --- a/passes/cmds/show.cc +++ b/passes/cmds/show.cc @@ -337,7 +337,7 @@ struct ShowWorker fprintf(f, "}\n"); } - for (auto &it : module->cells) + for (auto &it : module->cells_) { if (!design->selected_member(module->name, it.first)) continue; @@ -516,7 +516,7 @@ struct ShowWorker log("Skipping blackbox module %s.\n", id2cstr(module->name)); continue; } else - if (module->cells.empty() && module->connections().empty() && module->processes.empty()) { + if (module->cells_.empty() && module->connections().empty() && module->processes.empty()) { log("Skipping empty module %s.\n", id2cstr(module->name)); continue; } else @@ -695,7 +695,7 @@ struct ShowPass : public Pass { for (auto &mod_it : design->modules) { if (mod_it.second->get_bool_attribute("\\blackbox")) continue; - if (mod_it.second->cells.empty() && mod_it.second->connections().empty()) + if (mod_it.second->cells_.empty() && mod_it.second->connections().empty()) continue; if (design->selected_module(mod_it.first)) modcount++; |