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authorRuben Undheim <ruben.undheim@gmail.com>2014-09-06 08:47:06 +0200
committerRuben Undheim <ruben.undheim@gmail.com>2014-09-06 08:47:06 +0200
commit79cbf9067c07ed810b3466174278d77b9a05b46d (patch)
treeb546123251d39df2ffd115fb0b8a08e57e7cf538 /passes/cmds/splice.cc
parent01ef34c147dd3e3e3d13864f9c726727a4013207 (diff)
Corrected spelling mistakes found by lintian
Diffstat (limited to 'passes/cmds/splice.cc')
-rw-r--r--passes/cmds/splice.cc4
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/cmds/splice.cc b/passes/cmds/splice.cc
index ca71f7d8..d03aaf3b 100644
--- a/passes/cmds/splice.cc
+++ b/passes/cmds/splice.cc
@@ -251,12 +251,12 @@ struct SplicePass : public Pass {
log("\n");
log(" -sel_by_cell\n");
log(" only select the cell ports to rewire by the cell. if the selection\n");
- log(" contains a cell, than all cell inputs are rewired, if neccessary.\n");
+ log(" contains a cell, than all cell inputs are rewired, if necessary.\n");
log("\n");
log(" -sel_by_wire\n");
log(" only select the cell ports to rewire by the wire. if the selection\n");
log(" contains a wire, than all cell ports driven by this wire are wired,\n");
- log(" if neccessary.\n");
+ log(" if necessary.\n");
log("\n");
log(" -sel_any_bit\n");
log(" it is sufficient if the driver of any bit of a cell port is selected.\n");