diff options
author | Clifford Wolf <clifford@clifford.at> | 2014-07-26 14:32:50 +0200 |
---|---|---|
committer | Clifford Wolf <clifford@clifford.at> | 2014-07-26 15:58:23 +0200 |
commit | b7dda723022ad00c6c0089be888eab319953faa8 (patch) | |
tree | 4fe12ce120f1809891dc4cbd862bbcdab0e90fcc /passes/cmds/splice.cc | |
parent | cd6574ecf652901573cbc6b89e1a59dd383ec496 (diff) |
Changed users of cell->connections_ to the new API (sed command)
git grep -l 'connections_' | xargs sed -i -r -e '
s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g;
s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g;
s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g;
s/(->|\.)connections_.push_back/\1connect/g;
s/(->|\.)connections_/\1connections()/g;'
Diffstat (limited to 'passes/cmds/splice.cc')
-rw-r--r-- | passes/cmds/splice.cc | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/passes/cmds/splice.cc b/passes/cmds/splice.cc index c8b3d0b0..94f8365b 100644 --- a/passes/cmds/splice.cc +++ b/passes/cmds/splice.cc @@ -74,9 +74,9 @@ struct SpliceWorker cell->parameters["\\OFFSET"] = offset; cell->parameters["\\A_WIDTH"] = sig_a.size(); cell->parameters["\\Y_WIDTH"] = sig.size(); - cell->connections_["\\A"] = sig_a; - cell->connections_["\\Y"] = module->addWire(NEW_ID, sig.size()); - new_sig = cell->connections_["\\Y"]; + cell->set("\\A", sig_a); + cell->set("\\Y", module->addWire(NEW_ID, sig.size())); + new_sig = cell->get("\\Y"); } sliced_signals_cache[sig] = new_sig; @@ -130,10 +130,10 @@ struct SpliceWorker RTLIL::Cell *cell = module->addCell(NEW_ID, "$concat"); cell->parameters["\\A_WIDTH"] = new_sig.size(); cell->parameters["\\B_WIDTH"] = sig2.size(); - cell->connections_["\\A"] = new_sig; - cell->connections_["\\B"] = sig2; - cell->connections_["\\Y"] = module->addWire(NEW_ID, new_sig.size() + sig2.size()); - new_sig = cell->connections_["\\Y"]; + cell->set("\\A", new_sig); + cell->set("\\B", sig2); + cell->set("\\Y", module->addWire(NEW_ID, new_sig.size() + sig2.size())); + new_sig = cell->get("\\Y"); } spliced_signals_cache[sig] = new_sig; @@ -159,7 +159,7 @@ struct SpliceWorker } for (auto &it : module->cells) - for (auto &conn : it.second->connections_) + for (auto &conn : it.second->connections()) if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first)) { RTLIL::SigSpec sig = sigmap(conn.second); driven_chunks.insert(sig); @@ -182,7 +182,7 @@ struct SpliceWorker for (auto &it : module->cells) { if (!sel_by_wire && !design->selected(module, it.second)) continue; - for (auto &conn : it.second->connections_) + for (auto &conn : it.second->connections()) if (ct.cell_input(it.second->type, conn.first)) { if (ports.size() > 0 && !ports.count(conn.first)) continue; @@ -232,7 +232,7 @@ struct SpliceWorker it.first->port_output = false; module->add(it.first); module->add(new_port); - module->connections_.push_back(RTLIL::SigSig(new_port, it.second)); + module->connect(RTLIL::SigSig(new_port, it.second)); } } }; |