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authorClifford Wolf <clifford@clifford.at>2015-08-14 10:56:05 +0200
committerClifford Wolf <clifford@clifford.at>2015-08-14 10:56:05 +0200
commit84bf862f7c58c2b69babf043ff5032f924a3ee4d (patch)
treec19a405bc106c2472f1aaa46c36b189db3e5223f /passes/cmds
parent80910d13a610886f4430fbd991ada78b2e586ada (diff)
Spell check (by Larry Doolittle)
Diffstat (limited to 'passes/cmds')
-rw-r--r--passes/cmds/check.cc2
-rw-r--r--passes/cmds/connect.cc2
-rw-r--r--passes/cmds/connwrappers.cc4
-rw-r--r--passes/cmds/design.cc2
-rw-r--r--passes/cmds/select.cc4
-rw-r--r--passes/cmds/show.cc14
-rw-r--r--passes/cmds/splice.cc2
-rw-r--r--passes/cmds/write_file.cc2
8 files changed, 16 insertions, 16 deletions
diff --git a/passes/cmds/check.cc b/passes/cmds/check.cc
index fe74408d..2ad84838 100644
--- a/passes/cmds/check.cc
+++ b/passes/cmds/check.cc
@@ -35,7 +35,7 @@ struct CheckPass : public Pass {
log("\n");
log("This pass identifies the following problems in the current design:\n");
log("\n");
- log(" - combinatorical loops\n");
+ log(" - combinatorial loops\n");
log("\n");
log(" - two or more conflicting drivers for one wire\n");
log("\n");
diff --git a/passes/cmds/connect.cc b/passes/cmds/connect.cc
index e09d636f..e0b1ce05 100644
--- a/passes/cmds/connect.cc
+++ b/passes/cmds/connect.cc
@@ -49,7 +49,7 @@ struct ConnectPass : public Pass {
log("\n");
log(" connect [-nomap] [-nounset] -set <lhs-expr> <rhs-expr>\n");
log("\n");
- log("Create a connection. This is equivialent to adding the statement 'assign\n");
+ log("Create a connection. This is equivalent to adding the statement 'assign\n");
log("<lhs-expr> = <rhs-expr>;' to the verilog input. Per default, all existing\n");
log("drivers for <lhs-expr> are unconnected. This can be overwritten by using\n");
log("the -nounset option.\n");
diff --git a/passes/cmds/connwrappers.cc b/passes/cmds/connwrappers.cc
index 1c66fb81..7828dce1 100644
--- a/passes/cmds/connwrappers.cc
+++ b/passes/cmds/connwrappers.cc
@@ -158,8 +158,8 @@ struct ConnwrappersPass : public Pass {
log("\n");
log("Wrappers are used in coarse-grain synthesis to wrap cells with smaller ports\n");
log("in wrapper cells with a (larger) constant port size. I.e. the upper bits\n");
- log("of the wrapper outut are signed/unsigned bit extended. This command uses this\n");
- log("knowlege to rewire the inputs of the driven cells to match the output of\n");
+ log("of the wrapper output are signed/unsigned bit extended. This command uses this\n");
+ log("knowledge to rewire the inputs of the driven cells to match the output of\n");
log("the driving cell.\n");
log("\n");
log(" -signed <cell_type> <port_name> <width_param>\n");
diff --git a/passes/cmds/design.cc b/passes/cmds/design.cc
index 16a4e64a..e900e7b9 100644
--- a/passes/cmds/design.cc
+++ b/passes/cmds/design.cc
@@ -80,7 +80,7 @@ struct DesignPass : public Pass {
log("\n");
log(" design -copy-to <name> [-as <new_mod_name>] [selection]\n");
log("\n");
- log("Copy modules from the current design into the soecified one.\n");
+ log("Copy modules from the current design into the specified one.\n");
log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc
index c9268165..b4219db2 100644
--- a/passes/cmds/select.cc
+++ b/passes/cmds/select.cc
@@ -1078,7 +1078,7 @@ struct SelectPass : public Pass {
log("\n");
log(" %%ci[<num1>|*][.<num2>][:<rule>[:<rule>..]]\n");
log(" %%co[<num1>|*][.<num2>][:<rule>[:<rule>..]]\n");
- log(" simmilar to %%x, but only select input (%%ci) or output cones (%%co)\n");
+ log(" similar to %%x, but only select input (%%ci) or output cones (%%co)\n");
log("\n");
log(" %%xe[...] %%cie[...] %%coe\n");
log(" like %%x, %%ci, and %%co but only consider combinatorial cells\n");
@@ -1403,7 +1403,7 @@ struct CdPass : public Pass {
log(" cd <cellname>\n");
log("\n");
log("When no module with the specified name is found, but there is a cell\n");
- log("with the specified name in the current module, then this is equivialent\n");
+ log("with the specified name in the current module, then this is equivalent\n");
log("to 'cd <celltype>'.\n");
log("\n");
log(" cd ..\n");
diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc
index 28e3decd..3035e730 100644
--- a/passes/cmds/show.cc
+++ b/passes/cmds/show.cc
@@ -610,7 +610,7 @@ struct ShowPass : public Pass {
log(" -colors <seed>\n");
log(" Randomly assign colors to the wires. The integer argument is the seed\n");
log(" for the random number generator. Change the seed value if the colored\n");
- log(" graph still is ambigous. A seed of zero deactivates the coloring.\n");
+ log(" graph still is ambiguous. A seed of zero deactivates the coloring.\n");
log("\n");
log(" -colorattr <attribute_name>\n");
log(" Use the specified attribute to assign colors. A unique color is\n");
@@ -620,7 +620,7 @@ struct ShowPass : public Pass {
log(" annotate busses with a label indicating the width of the bus.\n");
log("\n");
log(" -signed\n");
- log(" mark ports (A, B) that are declarted as signed (using the [AB]_SIGNED\n");
+ log(" mark ports (A, B) that are declared as signed (using the [AB]_SIGNED\n");
log(" cell parameter) with an asterisk next to the port name.\n");
log("\n");
log(" -stretch\n");
@@ -634,7 +634,7 @@ struct ShowPass : public Pass {
log(" enumerate objects with internal ($-prefixed) names\n");
log("\n");
log(" -long\n");
- log(" do not abbeviate objects with internal ($-prefixed) names\n");
+ log(" do not abbreviate objects with internal ($-prefixed) names\n");
log("\n");
log(" -notitle\n");
log(" do not add the module name as graph title to the dot file\n");
@@ -673,7 +673,7 @@ struct ShowPass : public Pass {
bool flag_stretch = false;
bool flag_pause = false;
bool flag_enum = false;
- bool flag_abbeviate = true;
+ bool flag_abbreviate = true;
bool flag_notitle = false;
RTLIL::IdString colorattr;
@@ -743,12 +743,12 @@ struct ShowPass : public Pass {
}
if (arg == "-enum") {
flag_enum = true;
- flag_abbeviate = false;
+ flag_abbreviate = false;
continue;
}
if (arg == "-long") {
flag_enum = false;
- flag_abbeviate = false;
+ flag_abbreviate = false;
continue;
}
if (arg == "-notitle") {
@@ -796,7 +796,7 @@ struct ShowPass : public Pass {
delete lib;
log_cmd_error("Can't open dot file `%s' for writing.\n", dot_file.c_str());
}
- ShowWorker worker(f, design, libs, colorSeed, flag_width, flag_signed, flag_stretch, flag_enum, flag_abbeviate, flag_notitle, color_selections, label_selections, colorattr);
+ ShowWorker worker(f, design, libs, colorSeed, flag_width, flag_signed, flag_stretch, flag_enum, flag_abbreviate, flag_notitle, color_selections, label_selections, colorattr);
fclose(f);
for (auto lib : libs)
diff --git a/passes/cmds/splice.cc b/passes/cmds/splice.cc
index e56699f4..4ce2ec11 100644
--- a/passes/cmds/splice.cc
+++ b/passes/cmds/splice.cc
@@ -255,7 +255,7 @@ struct SplicePass : public Pass {
log("\n");
log("This command adds $slice and $concat cells to the design to make the splicing\n");
log("of multi-bit signals explicit. This for example is useful for coarse grain\n");
- log("synthesis, where dedidacted hardware is needed to splice signals.\n");
+ log("synthesis, where dedicated hardware is needed to splice signals.\n");
log("\n");
log(" -sel_by_cell\n");
log(" only select the cell ports to rewire by the cell. if the selection\n");
diff --git a/passes/cmds/write_file.cc b/passes/cmds/write_file.cc
index 25ec4acc..b7826593 100644
--- a/passes/cmds/write_file.cc
+++ b/passes/cmds/write_file.cc
@@ -31,7 +31,7 @@ struct WriteFileFrontend : public Frontend {
log("\n");
log(" write_file [options] output_file [input_file]\n");
log("\n");
- log("Write the text fron the input file to the output file.\n");
+ log("Write the text from the input file to the output file.\n");
log("\n");
log(" -a\n");
log(" Append to output file (instead of overwriting)\n");