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authorClifford Wolf <clifford@clifford.at>2015-10-24 22:56:40 +0200
committerClifford Wolf <clifford@clifford.at>2015-10-24 22:56:40 +0200
commit7f110e7018d35f29cf6a5d3031400a8044c8d32d (patch)
tree9c65e6929e43faec716efab17b37bd53f9afa4b3 /passes/equiv/equiv_simple.cc
parent6af80769678f260aa4aeaf3b12b54dfdc15fa5dd (diff)
renamed SigSpec::to_single_sigbit() to SigSpec::as_bit(), added is_bit()
Diffstat (limited to 'passes/equiv/equiv_simple.cc')
-rw-r--r--passes/equiv/equiv_simple.cc6
1 files changed, 3 insertions, 3 deletions
diff --git a/passes/equiv/equiv_simple.cc b/passes/equiv/equiv_simple.cc
index 1f52a632..fa22dc62 100644
--- a/passes/equiv/equiv_simple.cc
+++ b/passes/equiv/equiv_simple.cc
@@ -89,8 +89,8 @@ struct EquivSimpleWorker
bool run_cell()
{
- SigBit bit_a = sigmap(equiv_cell->getPort("\\A")).to_single_sigbit();
- SigBit bit_b = sigmap(equiv_cell->getPort("\\B")).to_single_sigbit();
+ SigBit bit_a = sigmap(equiv_cell->getPort("\\A")).as_bit();
+ SigBit bit_b = sigmap(equiv_cell->getPort("\\B")).as_bit();
int ez_context = ez->frozen_literal();
if (satgen.model_undef)
@@ -314,7 +314,7 @@ struct EquivSimplePass : public Pass {
for (auto cell : module->selected_cells())
if (cell->type == "$equiv" && cell->getPort("\\A") != cell->getPort("\\B")) {
- auto bit = sigmap(cell->getPort("\\Y").to_single_sigbit());
+ auto bit = sigmap(cell->getPort("\\Y").as_bit());
auto bit_group = bit;
if (!nogroup && bit_group.wire)
bit_group.offset = 0;