diff options
| author | Clifford Wolf <clifford@clifford.at> | 2015-10-24 23:04:17 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-10-24 23:04:17 +0200 |
| commit | 453736d91878de840714024b0fde416bc6af8215 (patch) | |
| tree | b86b8b1f742122fd688cb23a72d8a703cacad872 /passes/equiv | |
| parent | 7f110e7018d35f29cf6a5d3031400a8044c8d32d (diff) | |
Improvements in equiv_struct
Diffstat (limited to 'passes/equiv')
| -rw-r--r-- | passes/equiv/equiv_struct.cc | 23 |
1 files changed, 22 insertions, 1 deletions
diff --git a/passes/equiv/equiv_struct.cc b/passes/equiv/equiv_struct.cc index c509e255..d231913c 100644 --- a/passes/equiv/equiv_struct.cc +++ b/passes/equiv/equiv_struct.cc @@ -116,9 +116,15 @@ struct EquivStructWorker { log(" Starting new iteration.\n"); + pool<SigBit> equiv_inputs; + for (auto cell : module->selected_cells()) if (cell->type == "$equiv") { - equiv_bits.add(sigmap(cell->getPort("\\A")), sigmap(cell->getPort("\\B"))); + SigBit sig_a = sigmap(cell->getPort("\\A").as_bit()); + SigBit sig_b = sigmap(cell->getPort("\\B").as_bit()); + equiv_bits.add(sig_b, sig_a); + equiv_inputs.insert(sig_a); + equiv_inputs.insert(sig_b); cells_by_type[cell->type].insert(cell->name); } else if (module->design->selected(module, cell)) { @@ -126,6 +132,21 @@ struct EquivStructWorker cells_by_type[cell->type].insert(cell->name); } + for (auto cell_name : cells_by_type["$equiv"]) { + Cell *cell = module->cell(cell_name); + SigBit sig_a = sigmap(cell->getPort("\\A").as_bit()); + SigBit sig_b = sigmap(cell->getPort("\\B").as_bit()); + SigBit sig_y = sigmap(cell->getPort("\\Y").as_bit()); + if (sig_a == sig_b && equiv_inputs.count(sig_y)) { + log(" Purging redundant $equiv cell %s.\n", log_id(cell)); + module->remove(cell); + merge_count++; + } + } + + if (merge_count > 0) + return; + for (auto &it : cells_by_type) { if (it.second.size() <= 1) |