diff options
| author | Clifford Wolf <clifford@clifford.at> | 2013-03-05 12:53:40 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-03-05 12:53:40 +0100 |
| commit | 334fd03e1ccdc7e6330672318679a225b257e553 (patch) | |
| tree | f9d9aa1be9f161808fb64fd48e7a2fb91d782588 /passes/extract | |
| parent | efbb89de1a02806c0d6aa05eef5e80ea683f27ac (diff) | |
Implemented much better #x select operator
Diffstat (limited to 'passes/extract')
| -rw-r--r-- | passes/extract/extract.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/passes/extract/extract.cc b/passes/extract/extract.cc index 66910861..62d09523 100644 --- a/passes/extract/extract.cc +++ b/passes/extract/extract.cc @@ -121,6 +121,9 @@ namespace if (max_fanout > 0 && sig_use_count[std::pair<RTLIL::Wire*, int>(chunk.wire, chunk.offset)] > max_fanout) continue; + if (sel && !sel->selected(mod, chunk.wire)) + continue; + if (sig_bit_ref.count(chunk) == 0) { bit_ref_t &bit_ref = sig_bit_ref[chunk]; bit_ref.cell = cell->name; @@ -308,9 +311,6 @@ struct ExtractPass : public Pass { log("integer value. Then this value is used to determine the order in which the pass\n"); log("tries to map the modules to the design (ascending, default value is 0).\n"); log("\n"); - log("This pass operates on whole modules or selected cells from modules. Other\n"); - log("selected entities (wires, etc.) are ignored.\n"); - log("\n"); log("See 'help techmap' for a pass that does the opposite thing.\n"); log("\n"); } |