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authorClifford Wolf <clifford@clifford.at>2014-08-14 11:39:46 +0200
committerClifford Wolf <clifford@clifford.at>2014-08-14 11:39:46 +0200
commit13f2f36884fa3e4a8329dab2556af7000cb085df (patch)
tree59787125c75220ee6f78d160e6cc6cfcc583d0ec /passes/fsm/fsm_detect.cc
parent28cf48e31f049f8343023de46cd916ac47fcfc5d (diff)
RIP $safe_pmux
Diffstat (limited to 'passes/fsm/fsm_detect.cc')
-rw-r--r--passes/fsm/fsm_detect.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/fsm/fsm_detect.cc b/passes/fsm/fsm_detect.cc
index 5675dff5..2c846a4c 100644
--- a/passes/fsm/fsm_detect.cc
+++ b/passes/fsm/fsm_detect.cc
@@ -50,7 +50,7 @@ static bool check_state_mux_tree(RTLIL::SigSpec old_sig, RTLIL::SigSpec sig, Sig
std::set<sig2driver_entry_t> cellport_list;
sig2driver.find(sig, cellport_list);
for (auto &cellport : cellport_list) {
- if ((cellport.first->type != "$mux" && cellport.first->type != "$pmux" && cellport.first->type != "$safe_pmux") || cellport.second != "\\Y")
+ if ((cellport.first->type != "$mux" && cellport.first->type != "$pmux") || cellport.second != "\\Y")
return false;
RTLIL::SigSpec sig_a = assign_map(cellport.first->getPort("\\A"));
RTLIL::SigSpec sig_b = assign_map(cellport.first->getPort("\\B"));