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authorClifford Wolf <clifford@clifford.at>2014-07-22 19:56:17 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-22 20:39:37 +0200
commita233762a815fc180b371f699e865a7d7aed77bca (patch)
tree722e54921bbc09595c046c6045cd531445945fc9 /passes/fsm/fsm_detect.cc
parent3b5f4ff39c94a5a664043f35b95a50240ffe9d12 (diff)
SigSpec refactoring: renamed chunks and width to __chunks and __width
Diffstat (limited to 'passes/fsm/fsm_detect.cc')
-rw-r--r--passes/fsm/fsm_detect.cc4
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/fsm/fsm_detect.cc b/passes/fsm/fsm_detect.cc
index a8ec1912..523feae9 100644
--- a/passes/fsm/fsm_detect.cc
+++ b/passes/fsm/fsm_detect.cc
@@ -56,8 +56,8 @@ static bool check_state_mux_tree(RTLIL::SigSpec old_sig, RTLIL::SigSpec sig, Sig
RTLIL::SigSpec sig_b = assign_map(cellport.first->connections["\\B"]);
if (!check_state_mux_tree(old_sig, sig_a, recursion_monitor))
return false;
- for (int i = 0; i < sig_b.width; i += sig_a.width)
- if (!check_state_mux_tree(old_sig, sig_b.extract(i, sig_a.width), recursion_monitor))
+ for (int i = 0; i < sig_b.__width; i += sig_a.__width)
+ if (!check_state_mux_tree(old_sig, sig_b.extract(i, sig_a.__width), recursion_monitor))
return false;
muxtree_cells.insert(cellport.first);
}