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authorRuben Undheim <ruben.undheim@gmail.com>2019-03-28 23:35:03 +0100
committerRuben Undheim <ruben.undheim@gmail.com>2019-03-28 23:35:03 +0100
commitff5734b20220e6fb4a3913cf5279ed94bb5156ea (patch)
tree4c438282926d7bac304ad3ad6ad89523c4c1d784 /passes/fsm/fsm_detect.cc
parentdb3c67fd6e140893450a44870ee9a75dd1f48b27 (diff)
Imported GIT HEAD: 0.8+20190328git32bd0f2
Diffstat (limited to 'passes/fsm/fsm_detect.cc')
-rw-r--r--passes/fsm/fsm_detect.cc8
1 files changed, 4 insertions, 4 deletions
diff --git a/passes/fsm/fsm_detect.cc b/passes/fsm/fsm_detect.cc
index fc504e98..5ae991b2 100644
--- a/passes/fsm/fsm_detect.cc
+++ b/passes/fsm/fsm_detect.cc
@@ -196,13 +196,13 @@ static void detect_fsm(RTLIL::Wire *wire)
vector<string> warnings;
if (is_module_port)
- warnings.push_back("Forcing fsm recoding on module port might result in larger circuit.\n");
+ warnings.push_back("Forcing FSM recoding on module port might result in larger circuit.\n");
if (!looks_like_good_state_reg)
- warnings.push_back("Users of state reg look like fsm recoding might result in larger circuit.\n");
+ warnings.push_back("Users of state reg look like FSM recoding might result in larger circuit.\n");
if (has_init_attr)
- warnings.push_back("Init value on fsm state registers are ignored. Possible simulation-synthesis mismatch!");
+ warnings.push_back("Initialization value on FSM state register is ignored. Possible simulation-synthesis mismatch!\n");
if (!looks_like_state_reg)
warnings.push_back("Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!\n");
@@ -236,7 +236,7 @@ static void detect_fsm(RTLIL::Wire *wire)
log(" Users of register don't seem to benefit from recoding.\n");
if (has_init_attr)
- log(" Register has an initialization value.");
+ log(" Register has an initialization value.\n");
if (is_self_resetting)
log(" Circuit seems to be self-resetting.\n");