diff options
author | Clifford Wolf <clifford@clifford.at> | 2014-07-31 13:19:47 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-07-31 13:19:47 +0200 |
commit | 1cb25c05b37b0172dbc50e140fe20f25d973dd8a (patch) | |
tree | 4bccb9f45ccad05346697c79afca9a1b21dced9c /passes/fsm/fsm_extract.cc | |
parent | 1202f7aa4bb0f9afde157ebc4701d64e7e38abd8 (diff) |
Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace
Diffstat (limited to 'passes/fsm/fsm_extract.cc')
-rw-r--r-- | passes/fsm/fsm_extract.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc index 6da46832..718f779b 100644 --- a/passes/fsm/fsm_extract.cc +++ b/passes/fsm/fsm_extract.cc @@ -270,7 +270,7 @@ static void extract_fsm(RTLIL::Wire *wire) // create fsm cell - RTLIL::Cell *fsm_cell = module->addCell(stringf("$fsm$%s$%d", wire->name.c_str(), RTLIL::autoidx++), "$fsm"); + RTLIL::Cell *fsm_cell = module->addCell(stringf("$fsm$%s$%d", wire->name.c_str(), autoidx++), "$fsm"); fsm_cell->set("\\CLK", clk); fsm_cell->set("\\ARST", arst); fsm_cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity ? 1 : 0, 1); @@ -296,7 +296,7 @@ static void extract_fsm(RTLIL::Wire *wire) RTLIL::Cell *cell = module->cells_.at(cellport.first); RTLIL::SigSpec port_sig = assign_map(cell->get(cellport.second)); RTLIL::SigSpec unconn_sig = port_sig.extract(ctrl_out); - RTLIL::Wire *unconn_wire = module->addWire(stringf("$fsm_unconnect$%s$%d", log_signal(unconn_sig), RTLIL::autoidx++), unconn_sig.size()); + RTLIL::Wire *unconn_wire = module->addWire(stringf("$fsm_unconnect$%s$%d", log_signal(unconn_sig), autoidx++), unconn_sig.size()); port_sig.replace(unconn_sig, RTLIL::SigSpec(unconn_wire), &cell->connections_[cellport.second]); } } |