diff options
| author | Clifford Wolf <clifford@clifford.at> | 2014-08-14 11:39:46 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-08-14 11:39:46 +0200 |
| commit | 13f2f36884fa3e4a8329dab2556af7000cb085df (patch) | |
| tree | 59787125c75220ee6f78d160e6cc6cfcc583d0ec /passes/fsm/fsm_extract.cc | |
| parent | 28cf48e31f049f8343023de46cd916ac47fcfc5d (diff) | |
RIP $safe_pmux
Diffstat (limited to 'passes/fsm/fsm_extract.cc')
| -rw-r--r-- | passes/fsm/fsm_extract.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc index ebe3073d..871478de 100644 --- a/passes/fsm/fsm_extract.cc +++ b/passes/fsm/fsm_extract.cc @@ -55,7 +55,7 @@ static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL for (auto &cellport : cellport_list) { RTLIL::Cell *cell = module->cells_.at(cellport.first); - if ((cell->type != "$mux" && cell->type != "$pmux" && cell->type != "$safe_pmux") || cellport.second != "\\Y") { + if ((cell->type != "$mux" && cell->type != "$pmux") || cellport.second != "\\Y") { log(" unexpected cell type %s (%s) found in state selection tree.\n", cell->type.c_str(), cell->name.c_str()); return false; } |