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authorClifford Wolf <clifford@clifford.at>2014-07-22 20:58:44 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-22 20:58:44 +0200
commit28b3fd05fa9cf6d469fdec95e247a7ffe5bc001d (patch)
tree9a847fc2fc608ce9ffbc947bcb18eea2205bb2d5 /passes/fsm/fsm_extract.cc
parent7bffde6abdaf6fc2ed090946442f90b2438e6126 (diff)
SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw()
Diffstat (limited to 'passes/fsm/fsm_extract.cc')
-rw-r--r--passes/fsm/fsm_extract.cc4
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc
index 701b09bd..c3bb1933 100644
--- a/passes/fsm/fsm_extract.cc
+++ b/passes/fsm/fsm_extract.cc
@@ -92,7 +92,7 @@ static RTLIL::Const sig2const(ConstEval &ce, RTLIL::SigSpec sig, RTLIL::State no
{
if (dont_care.size() > 0) {
sig.expand();
- for (auto &chunk : sig.chunks()) {
+ for (auto &chunk : sig.chunks_rw()) {
assert(chunk.width == 1);
if (dont_care.extract(chunk).size() > 0)
chunk.wire = NULL, chunk.data = RTLIL::Const(noconst_state);
@@ -104,7 +104,7 @@ static RTLIL::Const sig2const(ConstEval &ce, RTLIL::SigSpec sig, RTLIL::State no
ce.values_map.apply(sig);
sig.expand();
- for (auto &chunk : sig.chunks()) {
+ for (auto &chunk : sig.chunks_rw()) {
assert(chunk.width == 1);
if (chunk.wire != NULL)
chunk.wire = NULL, chunk.data = RTLIL::Const(noconst_state);