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authorClifford Wolf <clifford@clifford.at>2015-07-02 11:14:30 +0200
committerClifford Wolf <clifford@clifford.at>2015-07-02 11:14:30 +0200
commit6c84341f22b2758181164e8d5cddd23e3589c90b (patch)
tree0438ad9becf956e43ebf8665fee89e021b13bcdf /passes/fsm/fsm_extract.cc
parent053058d78167f7f1ec377fddcee8b648a5ae4138 (diff)
Fixed trailing whitespaces
Diffstat (limited to 'passes/fsm/fsm_extract.cc')
-rw-r--r--passes/fsm/fsm_extract.cc8
1 files changed, 4 insertions, 4 deletions
diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc
index b5250970..7d68999f 100644
--- a/passes/fsm/fsm_extract.cc
+++ b/passes/fsm/fsm_extract.cc
@@ -2,11 +2,11 @@
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
- *
+ *
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
- *
+ *
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@@ -241,7 +241,7 @@ static void extract_fsm(RTLIL::Wire *wire)
{
log("Extracting FSM `%s' from module `%s'.\n", wire->name.c_str(), module->name.c_str());
- // get input and output signals for state ff
+ // get input and output signals for state ff
RTLIL::SigSpec dff_out = assign_map(RTLIL::SigSpec(wire));
RTLIL::SigSpec dff_in(RTLIL::State::Sm, wire->width);
@@ -460,5 +460,5 @@ struct FsmExtractPass : public Pass {
sig2trigger.clear();
}
} FsmExtractPass;
-
+
PRIVATE_NAMESPACE_END