diff options
| author | Clifford Wolf <clifford@clifford.at> | 2014-07-26 16:11:28 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-26 16:11:28 +0200 |
| commit | 97a59851a6c411ccb06162d4b31725bf89262378 (patch) | |
| tree | 74cba570ab858657b6fa524cdc9fa45b0493c4be /passes/fsm/fsm_extract.cc | |
| parent | a84cb0493566f8f5eb610c6d7b67dda85b0f227b (diff) | |
Added RTLIL::Cell::has(portname)
Diffstat (limited to 'passes/fsm/fsm_extract.cc')
| -rw-r--r-- | passes/fsm/fsm_extract.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc index e89bba89..ff3ac760 100644 --- a/passes/fsm/fsm_extract.cc +++ b/passes/fsm/fsm_extract.cc @@ -350,7 +350,7 @@ struct FsmExtractPass : public Pass { assign_map.apply(sig); sig2driver.insert(sig, sig2driver_entry_t(cell_it.first, conn_it.first)); } - if (ct.cell_input(cell_it.second->type, conn_it.first) && cell_it.second->connections().count("\\Y") > 0 && + if (ct.cell_input(cell_it.second->type, conn_it.first) && cell_it.second->has("\\Y") && cell_it.second->get("\\Y").size() == 1 && (conn_it.first == "\\A" || conn_it.first == "\\B")) { RTLIL::SigSpec sig = conn_it.second; assign_map.apply(sig); |