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authorClifford Wolf <clifford@clifford.at>2015-04-29 07:28:15 +0200
committerClifford Wolf <clifford@clifford.at>2015-04-29 07:28:15 +0200
commitf483dce7c231f83937b5944ed0166a70594a0e8b (patch)
treef9a2dc487da84ba9fcd53d8c56991b1dbe2dd7de /passes/fsm/fsm_extract.cc
parent9d067fecea8d17dc3e800d09973f5ddaae41774b (diff)
Added $eq/$neq -> $logic_not/$reduce_bool optimization
Diffstat (limited to 'passes/fsm/fsm_extract.cc')
-rw-r--r--passes/fsm/fsm_extract.cc4
1 files changed, 3 insertions, 1 deletions
diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc
index 68667ef0..b5250970 100644
--- a/passes/fsm/fsm_extract.cc
+++ b/passes/fsm/fsm_extract.cc
@@ -305,7 +305,9 @@ static void extract_fsm(RTLIL::Wire *wire)
for (auto &cellport : cellport_list) {
RTLIL::Cell *cell = module->cells_.at(cellport.first);
RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A"));
- RTLIL::SigSpec sig_b = assign_map(cell->getPort("\\B"));
+ RTLIL::SigSpec sig_b;
+ if (cell->hasPort("\\B"))
+ sig_b = assign_map(cell->getPort("\\B"));
RTLIL::SigSpec sig_y = assign_map(cell->getPort("\\Y"));
if (cellport.second == "\\A" && !sig_b.is_fully_const())
continue;