diff options
| author | Clifford Wolf <clifford@clifford.at> | 2014-07-27 10:18:00 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-27 11:18:30 +0200 |
| commit | 10e5791c5e5660cb784503d36439ee90d61eb06b (patch) | |
| tree | d7bd3d8f1d0254e14fcf68ce25545f42afab9724 /passes/fsm/fsm_info.cc | |
| parent | d088854b47f5f77c6a62be2ba4b895164938d7a2 (diff) | |
Refactoring: Renamed RTLIL::Design::modules to modules_
Diffstat (limited to 'passes/fsm/fsm_info.cc')
| -rw-r--r-- | passes/fsm/fsm_info.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/fsm/fsm_info.cc b/passes/fsm/fsm_info.cc index 4526939c..45d68a90 100644 --- a/passes/fsm/fsm_info.cc +++ b/passes/fsm/fsm_info.cc @@ -43,7 +43,7 @@ struct FsmInfoPass : public Pass { log_header("Executing FSM_INFO pass (dumping all available information on FSM cells).\n"); extra_args(args, 1, design); - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) if (design->selected(mod_it.second)) for (auto &cell_it : mod_it.second->cells_) if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second)) { |