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authorClifford Wolf <clifford@clifford.at>2014-07-27 01:51:45 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-27 01:51:45 +0200
commit4c4b6021562c598c4510831bd547edaa97d14dac (patch)
tree7d8bde9d617e67431bdb6c51b5e27ea1836fe7a5 /passes/fsm/fsm_info.cc
parentf9946232adf887e5aa4a48c64f88eaa17e424009 (diff)
Refactoring: Renamed RTLIL::Module::cells to cells_
Diffstat (limited to 'passes/fsm/fsm_info.cc')
-rw-r--r--passes/fsm/fsm_info.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/fsm/fsm_info.cc b/passes/fsm/fsm_info.cc
index f2d0c1a8..4526939c 100644
--- a/passes/fsm/fsm_info.cc
+++ b/passes/fsm/fsm_info.cc
@@ -45,7 +45,7 @@ struct FsmInfoPass : public Pass {
for (auto &mod_it : design->modules)
if (design->selected(mod_it.second))
- for (auto &cell_it : mod_it.second->cells)
+ for (auto &cell_it : mod_it.second->cells_)
if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second)) {
log("\n");
log("FSM `%s' from module `%s':\n", cell_it.second->name.c_str(), mod_it.first.c_str());