diff options
| author | Clifford Wolf <clifford@clifford.at> | 2014-10-10 16:59:44 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-10-10 17:07:24 +0200 |
| commit | 4569a747f8af3880e23408eb93323afc8088b78b (patch) | |
| tree | 81dcea51020173cd4951e8649f8bd8305e7c2591 /passes/fsm/fsm_map.cc | |
| parent | c7f5aab625bb90e766c1852592fdf42c951716c0 (diff) | |
Renamed SIZE() to GetSize() because of name collision on Win32
Diffstat (limited to 'passes/fsm/fsm_map.cc')
| -rw-r--r-- | passes/fsm/fsm_map.cc | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/passes/fsm/fsm_map.cc b/passes/fsm/fsm_map.cc index 2f6ac854..a260653f 100644 --- a/passes/fsm/fsm_map.cc +++ b/passes/fsm/fsm_map.cc @@ -30,8 +30,8 @@ PRIVATE_NAMESPACE_BEGIN static bool pattern_is_subset(const RTLIL::Const &super_pattern, const RTLIL::Const &sub_pattern) { - log_assert(SIZE(super_pattern.bits) == SIZE(sub_pattern.bits)); - for (int i = 0; i < SIZE(super_pattern.bits); i++) + log_assert(GetSize(super_pattern.bits) == GetSize(sub_pattern.bits)); + for (int i = 0; i < GetSize(super_pattern.bits); i++) if (sub_pattern.bits[i] == RTLIL::State::S0 || sub_pattern.bits[i] == RTLIL::State::S1) { if (super_pattern.bits[i] == RTLIL::State::S0 || super_pattern.bits[i] == RTLIL::State::S1) { if (super_pattern.bits[i] != sub_pattern.bits[i]) @@ -91,7 +91,7 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const if (pattern_is_subset(pattern, it2.first)) complete_in_state_cache.insert(it2.second.begin(), it2.second.end()); - if (SIZE(complete_in_state_cache) < num_states) + if (GetSize(complete_in_state_cache) < num_states) { if (or_sig.size() == 1) { @@ -226,7 +226,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) // generate next_state signal - if (SIZE(fsm_data.state_table) == 1) + if (GetSize(fsm_data.state_table) == 1) { module->connect(next_state_wire, fsm_data.state_table.front()); } |