Renamed port access function on RTLIL::Cell, added param access functions

6 files changed, 84 insertions, 84 deletions

diff --git a/passes/fsm/fsm_detect.cc b/passes/fsm/fsm_detect.cc
index a619cf57..6025de15 100644
--- a/passes/fsm/fsm_detect.cc
+++ b/passes/fsm/fsm_detect.cc
@@ -52,8 +52,8 @@ static bool check_state_mux_tree(RTLIL::SigSpec old_sig, RTLIL::SigSpec sig, Sig
 	for (auto &cellport : cellport_list) {
 		if ((cellport.first->type != "$mux" && cellport.first->type != "$pmux" && cellport.first->type != "$safe_pmux") || cellport.second != "\\Y")
 			return false;
-		RTLIL::SigSpec sig_a = assign_map(cellport.first->get("\\A"));
-		RTLIL::SigSpec sig_b = assign_map(cellport.first->get("\\B"));
+		RTLIL::SigSpec sig_a = assign_map(cellport.first->getPort("\\A"));
+		RTLIL::SigSpec sig_b = assign_map(cellport.first->getPort("\\B"));
 		if (!check_state_mux_tree(old_sig, sig_a, recursion_monitor))
 			return false;
 		for (int i = 0; i < sig_b.size(); i += sig_a.size())
@@ -80,14 +80,14 @@ static bool check_state_users(RTLIL::SigSpec sig)
 			continue;
 		if (cellport.second != "\\A" && cellport.second != "\\B")
 			return false;
-		if (!cell->has("\\A") || !cell->has("\\B") || !cell->has("\\Y"))
+		if (!cell->hasPort("\\A") || !cell->hasPort("\\B") || !cell->hasPort("\\Y"))
 			return false;
 		for (auto &port_it : cell->connections())
 			if (port_it.first != "\\A" && port_it.first != "\\B" && port_it.first != "\\Y")
 				return false;
-		if (assign_map(cell->get("\\A")) == sig && cell->get("\\B").is_fully_const())
+		if (assign_map(cell->getPort("\\A")) == sig && cell->getPort("\\B").is_fully_const())
 			continue;
-		if (assign_map(cell->get("\\B")) == sig && cell->get("\\A").is_fully_const())
+		if (assign_map(cell->getPort("\\B")) == sig && cell->getPort("\\A").is_fully_const())
 			continue;
 		return false;
 	}
@@ -109,8 +109,8 @@ static void detect_fsm(RTLIL::Wire *wire)
 			continue;
 		muxtree_cells.clear();
 		SigPool recursion_monitor;
-		RTLIL::SigSpec sig_q = assign_map(cellport.first->get("\\Q"));
-		RTLIL::SigSpec sig_d = assign_map(cellport.first->get("\\D"));
+		RTLIL::SigSpec sig_q = assign_map(cellport.first->getPort("\\Q"));
+		RTLIL::SigSpec sig_d = assign_map(cellport.first->getPort("\\D"));
 		if (sig_q == RTLIL::SigSpec(wire) && check_state_mux_tree(sig_q, sig_d, recursion_monitor) && check_state_users(sig_q)) {
 			log("Found FSM state register %s in module %s.\n", wire->name.c_str(), module->name.c_str());
 			wire->attributes["\\fsm_encoding"] = RTLIL::Const("auto");
diff --git a/passes/fsm/fsm_expand.cc b/passes/fsm/fsm_expand.cc
index 2da4794e..670fae1d 100644
--- a/passes/fsm/fsm_expand.cc
+++ b/passes/fsm/fsm_expand.cc
@@ -43,34 +43,34 @@ struct FsmExpand
 	bool is_cell_merge_candidate(RTLIL::Cell *cell)
 	{
 		if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$safe_pmux")
-			if (cell->get("\\A").size() < 2)
+			if (cell->getPort("\\A").size() < 2)
 				return true;
 
 		RTLIL::SigSpec new_signals;
-		if (cell->has("\\A"))
-			new_signals.append(assign_map(cell->get("\\A")));
-		if (cell->has("\\B"))
-			new_signals.append(assign_map(cell->get("\\B")));
-		if (cell->has("\\S"))
-			new_signals.append(assign_map(cell->get("\\S")));
-		if (cell->has("\\Y"))
-			new_signals.append(assign_map(cell->get("\\Y")));
+		if (cell->hasPort("\\A"))
+			new_signals.append(assign_map(cell->getPort("\\A")));
+		if (cell->hasPort("\\B"))
+			new_signals.append(assign_map(cell->getPort("\\B")));
+		if (cell->hasPort("\\S"))
+			new_signals.append(assign_map(cell->getPort("\\S")));
+		if (cell->hasPort("\\Y"))
+			new_signals.append(assign_map(cell->getPort("\\Y")));
 
 		new_signals.sort_and_unify();
 		new_signals.remove_const();
 
-		new_signals.remove(assign_map(fsm_cell->get("\\CTRL_IN")));
-		new_signals.remove(assign_map(fsm_cell->get("\\CTRL_OUT")));
+		new_signals.remove(assign_map(fsm_cell->getPort("\\CTRL_IN")));
+		new_signals.remove(assign_map(fsm_cell->getPort("\\CTRL_OUT")));
 
 		if (new_signals.size() > 3)
 			return false;
 
-		if (cell->has("\\Y")) {
-			new_signals.append(assign_map(cell->get("\\Y")));
+		if (cell->hasPort("\\Y")) {
+			new_signals.append(assign_map(cell->getPort("\\Y")));
 			new_signals.sort_and_unify();
 			new_signals.remove_const();
-			new_signals.remove(assign_map(fsm_cell->get("\\CTRL_IN")));
-			new_signals.remove(assign_map(fsm_cell->get("\\CTRL_OUT")));
+			new_signals.remove(assign_map(fsm_cell->getPort("\\CTRL_IN")));
+			new_signals.remove(assign_map(fsm_cell->getPort("\\CTRL_OUT")));
 		}
 
 		if (new_signals.size() > 2)
@@ -83,10 +83,10 @@ struct FsmExpand
 	{
 		std::vector<RTLIL::Cell*> cell_list;
 
-		for (auto c : sig2driver.find(assign_map(fsm_cell->get("\\CTRL_IN"))))
+		for (auto c : sig2driver.find(assign_map(fsm_cell->getPort("\\CTRL_IN"))))
 			cell_list.push_back(c);
 
-		for (auto c : sig2user.find(assign_map(fsm_cell->get("\\CTRL_OUT"))))
+		for (auto c : sig2user.find(assign_map(fsm_cell->getPort("\\CTRL_OUT"))))
 			cell_list.push_back(c);
 
 		current_set.clear();
@@ -148,12 +148,12 @@ struct FsmExpand
 		for (int i = 0; i < (1 << input_sig.size()); i++) {
 			RTLIL::Const in_val(i, input_sig.size());
 			RTLIL::SigSpec A, B, S;
-			if (cell->has("\\A"))
-				A = assign_map(cell->get("\\A"));
-			if (cell->has("\\B"))
-				B = assign_map(cell->get("\\B"));
-			if (cell->has("\\S"))
-				S = assign_map(cell->get("\\S"));
+			if (cell->hasPort("\\A"))
+				A = assign_map(cell->getPort("\\A"));
+			if (cell->hasPort("\\B"))
+				B = assign_map(cell->getPort("\\B"));
+			if (cell->hasPort("\\S"))
+				S = assign_map(cell->getPort("\\S"));
 			A.replace(input_sig, RTLIL::SigSpec(in_val));
 			B.replace(input_sig, RTLIL::SigSpec(in_val));
 			S.replace(input_sig, RTLIL::SigSpec(in_val));
@@ -167,14 +167,14 @@ struct FsmExpand
 		fsm_data.copy_from_cell(fsm_cell);
 
 		fsm_data.num_inputs += input_sig.size();
-		RTLIL::SigSpec new_ctrl_in = fsm_cell->get("\\CTRL_IN");
+		RTLIL::SigSpec new_ctrl_in = fsm_cell->getPort("\\CTRL_IN");
 		new_ctrl_in.append(input_sig);
-		fsm_cell->set("\\CTRL_IN", new_ctrl_in);
+		fsm_cell->setPort("\\CTRL_IN", new_ctrl_in);
 
 		fsm_data.num_outputs += output_sig.size();
-		RTLIL::SigSpec new_ctrl_out = fsm_cell->get("\\CTRL_OUT");
+		RTLIL::SigSpec new_ctrl_out = fsm_cell->getPort("\\CTRL_OUT");
 		new_ctrl_out.append(output_sig);
-		fsm_cell->set("\\CTRL_OUT", new_ctrl_out);
+		fsm_cell->setPort("\\CTRL_OUT", new_ctrl_out);
 
 		std::vector<FsmData::transition_t> new_transition_table;
 		for (auto &tr : fsm_data.transition_table) {
diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc
index 718f779b..cf2075fb 100644
--- a/passes/fsm/fsm_extract.cc
+++ b/passes/fsm/fsm_extract.cc
@@ -58,9 +58,9 @@ static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL
 			log("  unexpected cell type %s (%s) found in state selection tree.\n", cell->type.c_str(), cell->name.c_str());
 			return false;
 		}
-		RTLIL::SigSpec sig_a = assign_map(cell->get("\\A"));
-		RTLIL::SigSpec sig_b = assign_map(cell->get("\\B"));
-		RTLIL::SigSpec sig_s = assign_map(cell->get("\\S"));
+		RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A"));
+		RTLIL::SigSpec sig_b = assign_map(cell->getPort("\\B"));
+		RTLIL::SigSpec sig_s = assign_map(cell->getPort("\\S"));
 		if (reset_state && RTLIL::SigSpec(*reset_state).is_fully_undef())
 			do {
 				if (sig_a.is_fully_def())
@@ -183,12 +183,12 @@ static void extract_fsm(RTLIL::Wire *wire)
 		if ((cell->type != "$dff" && cell->type != "$adff") || cellport.second != "\\Q")
 			continue;
 		log("  found %s cell for state register: %s\n", cell->type.c_str(), cell->name.c_str());
-		RTLIL::SigSpec sig_q = assign_map(cell->get("\\Q"));
-		RTLIL::SigSpec sig_d = assign_map(cell->get("\\D"));
-		clk = cell->get("\\CLK");
+		RTLIL::SigSpec sig_q = assign_map(cell->getPort("\\Q"));
+		RTLIL::SigSpec sig_d = assign_map(cell->getPort("\\D"));
+		clk = cell->getPort("\\CLK");
 		clk_polarity = cell->parameters["\\CLK_POLARITY"].as_bool();
 		if (cell->type == "$adff") {
-			arst = cell->get("\\ARST");
+			arst = cell->getPort("\\ARST");
 			arst_polarity = cell->parameters["\\ARST_POLARITY"].as_bool();
 			reset_state = cell->parameters["\\ARST_VALUE"];
 		}
@@ -224,9 +224,9 @@ static void extract_fsm(RTLIL::Wire *wire)
 	sig2trigger.find(dff_out, cellport_list);
 	for (auto &cellport : cellport_list) {
 		RTLIL::Cell *cell = module->cells_.at(cellport.first);
-		RTLIL::SigSpec sig_a = assign_map(cell->get("\\A"));
-		RTLIL::SigSpec sig_b = assign_map(cell->get("\\B"));
-		RTLIL::SigSpec sig_y = assign_map(cell->get("\\Y"));
+		RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A"));
+		RTLIL::SigSpec sig_b = assign_map(cell->getPort("\\B"));
+		RTLIL::SigSpec sig_y = assign_map(cell->getPort("\\Y"));
 		if (cellport.second == "\\A" && !sig_b.is_fully_const())
 			continue;
 		if (cellport.second == "\\B" && !sig_a.is_fully_const())
@@ -271,12 +271,12 @@ static void extract_fsm(RTLIL::Wire *wire)
 	// create fsm cell
 
 	RTLIL::Cell *fsm_cell = module->addCell(stringf("$fsm$%s$%d", wire->name.c_str(), autoidx++), "$fsm");
-	fsm_cell->set("\\CLK", clk);
-	fsm_cell->set("\\ARST", arst);
+	fsm_cell->setPort("\\CLK", clk);
+	fsm_cell->setPort("\\ARST", arst);
 	fsm_cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity ? 1 : 0, 1);
 	fsm_cell->parameters["\\ARST_POLARITY"] = RTLIL::Const(arst_polarity ? 1 : 0, 1);
-	fsm_cell->set("\\CTRL_IN", ctrl_in);
-	fsm_cell->set("\\CTRL_OUT", ctrl_out);
+	fsm_cell->setPort("\\CTRL_IN", ctrl_in);
+	fsm_cell->setPort("\\CTRL_OUT", ctrl_out);
 	fsm_cell->parameters["\\NAME"] = RTLIL::Const(wire->name);
 	fsm_cell->attributes = wire->attributes;
 	fsm_data.copy_to_cell(fsm_cell);
@@ -294,7 +294,7 @@ static void extract_fsm(RTLIL::Wire *wire)
 	sig2driver.find(ctrl_out, cellport_list);
 	for (auto &cellport : cellport_list) {
 		RTLIL::Cell *cell = module->cells_.at(cellport.first);
-		RTLIL::SigSpec port_sig = assign_map(cell->get(cellport.second));
+		RTLIL::SigSpec port_sig = assign_map(cell->getPort(cellport.second));
 		RTLIL::SigSpec unconn_sig = port_sig.extract(ctrl_out);
 		RTLIL::Wire *unconn_wire = module->addWire(stringf("$fsm_unconnect$%s$%d", log_signal(unconn_sig), autoidx++), unconn_sig.size());
 		port_sig.replace(unconn_sig, RTLIL::SigSpec(unconn_wire), &cell->connections_[cellport.second]);
@@ -347,8 +347,8 @@ struct FsmExtractPass : public Pass {
 						assign_map.apply(sig);
 						sig2driver.insert(sig, sig2driver_entry_t(cell_it.first, conn_it.first));
 					}
-					if (ct.cell_input(cell_it.second->type, conn_it.first) && cell_it.second->has("\\Y") &&
-							cell_it.second->get("\\Y").size() == 1 && (conn_it.first == "\\A" || conn_it.first == "\\B")) {
+					if (ct.cell_input(cell_it.second->type, conn_it.first) && cell_it.second->hasPort("\\Y") &&
+							cell_it.second->getPort("\\Y").size() == 1 && (conn_it.first == "\\A" || conn_it.first == "\\B")) {
 						RTLIL::SigSpec sig = conn_it.second;
 						assign_map.apply(sig);
 						sig2trigger.insert(sig, sig2driver_entry_t(cell_it.first, conn_it.first));
diff --git a/passes/fsm/fsm_map.cc b/passes/fsm/fsm_map.cc
index 8b9ad6be..99b736c1 100644
--- a/passes/fsm/fsm_map.cc
+++ b/passes/fsm/fsm_map.cc
@@ -58,9 +58,9 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
 			and_sig.append(RTLIL::SigSpec(eq_wire));
 
 			RTLIL::Cell *eq_cell = module->addCell(NEW_ID, "$eq");
-			eq_cell->set("\\A", eq_sig_a);
-			eq_cell->set("\\B", eq_sig_b);
-			eq_cell->set("\\Y", RTLIL::SigSpec(eq_wire));
+			eq_cell->setPort("\\A", eq_sig_a);
+			eq_cell->setPort("\\B", eq_sig_b);
+			eq_cell->setPort("\\Y", RTLIL::SigSpec(eq_wire));
 			eq_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false);
 			eq_cell->parameters["\\B_SIGNED"] = RTLIL::Const(false);
 			eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(eq_sig_a.size());
@@ -80,8 +80,8 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
 				and_sig.append(RTLIL::SigSpec(or_wire));
 
 				RTLIL::Cell *or_cell = module->addCell(NEW_ID, "$reduce_or");
-				or_cell->set("\\A", or_sig);
-				or_cell->set("\\Y", RTLIL::SigSpec(or_wire));
+				or_cell->setPort("\\A", or_sig);
+				or_cell->setPort("\\Y", RTLIL::SigSpec(or_wire));
 				or_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false);
 				or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(or_sig.size());
 				or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
@@ -96,9 +96,9 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
 				cases_vector.append(RTLIL::SigSpec(and_wire));
 
 				RTLIL::Cell *and_cell = module->addCell(NEW_ID, "$and");
-				and_cell->set("\\A", and_sig.extract(0, 1));
-				and_cell->set("\\B", and_sig.extract(1, 1));
-				and_cell->set("\\Y", RTLIL::SigSpec(and_wire));
+				and_cell->setPort("\\A", and_sig.extract(0, 1));
+				and_cell->setPort("\\B", and_sig.extract(1, 1));
+				and_cell->setPort("\\Y", RTLIL::SigSpec(and_wire));
 				and_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false);
 				and_cell->parameters["\\B_SIGNED"] = RTLIL::Const(false);
 				and_cell->parameters["\\A_WIDTH"] = RTLIL::Const(1);
@@ -119,8 +119,8 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
 
 	if (cases_vector.size() > 1) {
 		RTLIL::Cell *or_cell = module->addCell(NEW_ID, "$reduce_or");
-		or_cell->set("\\A", cases_vector);
-		or_cell->set("\\Y", output);
+		or_cell->setPort("\\A", cases_vector);
+		or_cell->setPort("\\Y", output);
 		or_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false);
 		or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(cases_vector.size());
 		or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
@@ -138,8 +138,8 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
 	FsmData fsm_data;
 	fsm_data.copy_from_cell(fsm_cell);
 
-	RTLIL::SigSpec ctrl_in = fsm_cell->get("\\CTRL_IN");
-	RTLIL::SigSpec ctrl_out = fsm_cell->get("\\CTRL_OUT");
+	RTLIL::SigSpec ctrl_in = fsm_cell->getPort("\\CTRL_IN");
+	RTLIL::SigSpec ctrl_out = fsm_cell->getPort("\\CTRL_OUT");
 
 	// create state register
 
@@ -151,7 +151,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
 	RTLIL::Wire *next_state_wire = module->addWire(NEW_ID, fsm_data.state_bits);
 
 	RTLIL::Cell *state_dff = module->addCell(NEW_ID, "");
-	if (fsm_cell->get("\\ARST").is_fully_const()) {
+	if (fsm_cell->getPort("\\ARST").is_fully_const()) {
 		state_dff->type = "$dff";
 	} else {
 		state_dff->type = "$adff";
@@ -160,13 +160,13 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
 		for (auto &bit : state_dff->parameters["\\ARST_VALUE"].bits)
 			if (bit != RTLIL::State::S1)
 				bit = RTLIL::State::S0;
-		state_dff->set("\\ARST", fsm_cell->get("\\ARST"));
+		state_dff->setPort("\\ARST", fsm_cell->getPort("\\ARST"));
 	}
 	state_dff->parameters["\\WIDTH"] = RTLIL::Const(fsm_data.state_bits);
 	state_dff->parameters["\\CLK_POLARITY"] = fsm_cell->parameters["\\CLK_POLARITY"];
-	state_dff->set("\\CLK", fsm_cell->get("\\CLK"));
-	state_dff->set("\\D", RTLIL::SigSpec(next_state_wire));
-	state_dff->set("\\Q", RTLIL::SigSpec(state_wire));
+	state_dff->setPort("\\CLK", fsm_cell->getPort("\\CLK"));
+	state_dff->setPort("\\D", RTLIL::SigSpec(next_state_wire));
+	state_dff->setPort("\\Q", RTLIL::SigSpec(state_wire));
 
 	// decode state register
 
@@ -194,9 +194,9 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
 			encoding_is_onehot = false;
 
 			RTLIL::Cell *eq_cell = module->addCell(NEW_ID, "$eq");
-			eq_cell->set("\\A", sig_a);
-			eq_cell->set("\\B", sig_b);
-			eq_cell->set("\\Y", RTLIL::SigSpec(state_onehot, i));
+			eq_cell->setPort("\\A", sig_a);
+			eq_cell->setPort("\\B", sig_b);
+			eq_cell->setPort("\\Y", RTLIL::SigSpec(state_onehot, i));
 			eq_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false);
 			eq_cell->parameters["\\B_SIGNED"] = RTLIL::Const(false);
 			eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_a.size());
@@ -260,10 +260,10 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
 		}
 
 		RTLIL::Cell *mux_cell = module->addCell(NEW_ID, "$safe_pmux");
-		mux_cell->set("\\A", sig_a);
-		mux_cell->set("\\B", sig_b);
-		mux_cell->set("\\S", sig_s);
-		mux_cell->set("\\Y", RTLIL::SigSpec(next_state_wire));
+		mux_cell->setPort("\\A", sig_a);
+		mux_cell->setPort("\\B", sig_b);
+		mux_cell->setPort("\\S", sig_s);
+		mux_cell->setPort("\\Y", RTLIL::SigSpec(next_state_wire));
 		mux_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_a.size());
 		mux_cell->parameters["\\S_WIDTH"] = RTLIL::Const(sig_s.size());
 	}
diff --git a/passes/fsm/fsm_opt.cc b/passes/fsm/fsm_opt.cc
index 9d9156ae..bcaa89bf 100644
--- a/passes/fsm/fsm_opt.cc
+++ b/passes/fsm/fsm_opt.cc
@@ -52,7 +52,7 @@ struct FsmOpt
 
 	void opt_const_and_unused_inputs()
 	{
-		RTLIL::SigSpec ctrl_in = cell->get("\\CTRL_IN");
+		RTLIL::SigSpec ctrl_in = cell->getPort("\\CTRL_IN");
 		std::vector<bool> ctrl_in_used(ctrl_in.size());
 
 		std::vector<FsmData::transition_t> new_transition_table;
@@ -73,15 +73,15 @@ struct FsmOpt
 
 		for (int i = int(ctrl_in_used.size())-1; i >= 0; i--) {
 			if (!ctrl_in_used[i]) {
-				log("  Removing unused input signal %s.\n", log_signal(cell->get("\\CTRL_IN").extract(i, 1)));
+				log("  Removing unused input signal %s.\n", log_signal(cell->getPort("\\CTRL_IN").extract(i, 1)));
 				for (auto &tr : new_transition_table) {
 					RTLIL::SigSpec tmp(tr.ctrl_in);
 					tmp.remove(i, 1);
 					tr.ctrl_in = tmp.as_const();
 				}
-				RTLIL::SigSpec new_ctrl_in = cell->get("\\CTRL_IN");
+				RTLIL::SigSpec new_ctrl_in = cell->getPort("\\CTRL_IN");
 				new_ctrl_in.remove(i, 1);
-				cell->set("\\CTRL_IN", new_ctrl_in);
+				cell->setPort("\\CTRL_IN", new_ctrl_in);
 				fsm_data.num_inputs--;
 			}
 		}
@@ -93,12 +93,12 @@ struct FsmOpt
 	void opt_unused_outputs()
 	{
 		for (int i = 0; i < fsm_data.num_outputs; i++) {
-			RTLIL::SigSpec sig = cell->get("\\CTRL_OUT").extract(i, 1);
+			RTLIL::SigSpec sig = cell->getPort("\\CTRL_OUT").extract(i, 1);
 			if (signal_is_unused(sig)) {
 				log("  Removing unused output signal %s.\n", log_signal(sig));
-				RTLIL::SigSpec new_ctrl_out = cell->get("\\CTRL_OUT");
+				RTLIL::SigSpec new_ctrl_out = cell->getPort("\\CTRL_OUT");
 				new_ctrl_out.remove(i, 1);
-				cell->set("\\CTRL_OUT", new_ctrl_out);
+				cell->setPort("\\CTRL_OUT", new_ctrl_out);
 				for (auto &tr : fsm_data.transition_table) {
 					RTLIL::SigSpec tmp(tr.ctrl_out);
 					tmp.remove(i, 1);
diff --git a/passes/fsm/fsmdata.h b/passes/fsm/fsmdata.h
index 8f0e5d62..7a44dd45 100644
--- a/passes/fsm/fsmdata.h
+++ b/passes/fsm/fsmdata.h
@@ -141,13 +141,13 @@ struct FsmData
 
 		log("\n");
 		log("  Input signals:\n");
-		RTLIL::SigSpec sig_in = cell->get("\\CTRL_IN");
+		RTLIL::SigSpec sig_in = cell->getPort("\\CTRL_IN");
 		for (int i = 0; i < SIZE(sig_in); i++)
 			log("  %3d: %s\n", i, log_signal(sig_in[i]));
 
 		log("\n");
 		log("  Output signals:\n");
-		RTLIL::SigSpec sig_out = cell->get("\\CTRL_OUT");
+		RTLIL::SigSpec sig_out = cell->getPort("\\CTRL_OUT");
 		for (int i = 0; i < SIZE(sig_out); i++)
 			log("  %3d: %s\n", i, log_signal(sig_out[i]));