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authorClifford Wolf <clifford@clifford.at>2013-03-15 10:23:02 +0100
committerClifford Wolf <clifford@clifford.at>2013-03-15 10:23:02 +0100
commit10956cb84aa7c3dd2300794b9283951dece9e5fa (patch)
treef61270ba49c58b0800885567fc489eaaa430f01a /passes/fsm
parent89f009d17187690fe0446fd95a1f623516a33f3d (diff)
Added [[CITE]] tags to abc and fsm_extract passes
Diffstat (limited to 'passes/fsm')
-rw-r--r--passes/fsm/fsm_extract.cc7
1 files changed, 6 insertions, 1 deletions
diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc
index 4971e4c1..10309316 100644
--- a/passes/fsm/fsm_extract.cc
+++ b/passes/fsm/fsm_extract.cc
@@ -17,6 +17,11 @@
*
*/
+// [[CITE]]
+// Yiqiong Shi; Chan Wai Ting; Bah-Hwee Gwee; Ye Ren, "A highly efficient method for extracting FSMs from flattened gate-level netlist,"
+// Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on , vol., no., pp.2610,2613, May 30 2010-June 2 2010
+// doi: 10.1109/ISCAS.2010.5537093
+
#include "kernel/log.h"
#include "kernel/register.h"
#include "kernel/sigtools.h"
@@ -283,7 +288,7 @@ static void extract_fsm(RTLIL::Wire *wire)
fsm_cell->connections["\\CTRL_IN"] = ctrl_in;
fsm_cell->connections["\\CTRL_OUT"] = ctrl_out;
fsm_cell->parameters["\\NAME"] = RTLIL::Const(wire->name);
- fsm_cell->attributes = wire->attributes;
+ fsm_cell->attributes = wire->attributes;
fsm_data.copy_to_cell(fsm_cell);
module->cells[fsm_cell->name] = fsm_cell;