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author | Ruben Undheim <ruben.undheim@gmail.com> | 2016-11-03 23:18:00 +0100 |
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committer | Ruben Undheim <ruben.undheim@gmail.com> | 2016-11-03 23:18:00 +0100 |
commit | fefe0fc0430f4f173a25e674708aa0f4f0854b31 (patch) | |
tree | adb13b830212c269d58031f900d652f29013d2d7 /passes/hierarchy/hierarchy.cc | |
parent | 4f096fe65b77435daba019248273e547fa18d167 (diff) |
Imported yosys 0.7
Diffstat (limited to 'passes/hierarchy/hierarchy.cc')
-rw-r--r-- | passes/hierarchy/hierarchy.cc | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 4d1e3987..e21a7a4e 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -212,6 +212,10 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check } else if (mod->wire(conn.first) == nullptr || mod->wire(conn.first)->port_id == 0) log_error("Module `%s' referenced in module `%s' in cell `%s' does not have a port named '%s'.\n", log_id(cell->type), log_id(module), log_id(cell), log_id(conn.first)); + for (auto ¶m : cell->parameters) + if (mod->avail_parameters.count(param.first) == 0 && param.first[0] != '$') + log_error("Module `%s' referenced in module `%s' in cell `%s' does not have a parameter named '%s'.\n", + log_id(cell->type), log_id(module), log_id(cell), log_id(param.first)); } if (cell->parameters.size() == 0) |