diff options
| author | Clifford Wolf <clifford@clifford.at> | 2014-07-27 10:18:00 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-27 11:18:30 +0200 |
| commit | 10e5791c5e5660cb784503d36439ee90d61eb06b (patch) | |
| tree | d7bd3d8f1d0254e14fcf68ce25545f42afab9724 /passes/hierarchy/submod.cc | |
| parent | d088854b47f5f77c6a62be2ba4b895164938d7a2 (diff) | |
Refactoring: Renamed RTLIL::Design::modules to modules_
Diffstat (limited to 'passes/hierarchy/submod.cc')
| -rw-r--r-- | passes/hierarchy/submod.cc | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc index 37410275..d32b5e1d 100644 --- a/passes/hierarchy/submod.cc +++ b/passes/hierarchy/submod.cc @@ -105,7 +105,7 @@ struct SubmodWorker RTLIL::Module *new_mod = new RTLIL::Module; new_mod->name = submod.full_name; - design->modules[new_mod->name] = new_mod; + design->modules_[new_mod->name] = new_mod; int port_counter = 1, auto_name_counter = 1; std::set<std::string> all_wire_names; @@ -229,7 +229,7 @@ struct SubmodWorker if (submodules.count(submod_str) == 0) { submodules[submod_str].name = submod_str; submodules[submod_str].full_name = module->name + "_" + submod_str; - while (design->modules.count(submodules[submod_str].full_name) != 0 || + while (design->modules_.count(submodules[submod_str].full_name) != 0 || module->count_id(submodules[submod_str].full_name) != 0) submodules[submod_str].full_name += "_"; } @@ -312,12 +312,12 @@ struct SubmodPass : public Pass { while (did_something) { did_something = false; std::vector<std::string> queued_modules; - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) if (handled_modules.count(mod_it.first) == 0 && design->selected_whole_module(mod_it.first)) queued_modules.push_back(mod_it.first); for (auto &modname : queued_modules) - if (design->modules.count(modname) != 0) { - SubmodWorker worker(design, design->modules[modname]); + if (design->modules_.count(modname) != 0) { + SubmodWorker worker(design, design->modules_[modname]); handled_modules.insert(modname); did_something = true; } @@ -328,7 +328,7 @@ struct SubmodPass : public Pass { else { RTLIL::Module *module = NULL; - for (auto &mod_it : design->modules) { + for (auto &mod_it : design->modules_) { if (!design->selected_module(mod_it.first)) continue; if (module != NULL) |