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authorClifford Wolf <clifford@clifford.at>2014-07-27 01:51:45 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-27 01:51:45 +0200
commit4c4b6021562c598c4510831bd547edaa97d14dac (patch)
tree7d8bde9d617e67431bdb6c51b5e27ea1836fe7a5 /passes/hierarchy/submod.cc
parentf9946232adf887e5aa4a48c64f88eaa17e424009 (diff)
Refactoring: Renamed RTLIL::Module::cells to cells_
Diffstat (limited to 'passes/hierarchy/submod.cc')
-rw-r--r--passes/hierarchy/submod.cc6
1 files changed, 3 insertions, 3 deletions
diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc
index 774aabae..37410275 100644
--- a/passes/hierarchy/submod.cc
+++ b/passes/hierarchy/submod.cc
@@ -87,7 +87,7 @@ struct SubmodWorker
flag_signal(conn.second, true, true, true, false, false);
}
}
- for (auto &it : module->cells) {
+ for (auto &it : module->cells_) {
RTLIL::Cell *cell = it.second;
if (submod.cells.count(cell) > 0)
continue;
@@ -215,7 +215,7 @@ struct SubmodWorker
for (auto &it : module->wires_)
it.second->attributes.erase("\\submod");
- for (auto &it : module->cells)
+ for (auto &it : module->cells_)
{
RTLIL::Cell *cell = it.second;
if (cell->attributes.count("\\submod") == 0 || cell->attributes["\\submod"].bits.size() == 0) {
@@ -239,7 +239,7 @@ struct SubmodWorker
}
else
{
- for (auto &it : module->cells)
+ for (auto &it : module->cells_)
{
RTLIL::Cell *cell = it.second;
if (!design->selected(module, cell))