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authorClifford Wolf <clifford@clifford.at>2014-08-14 16:13:42 +0200
committerClifford Wolf <clifford@clifford.at>2014-08-14 16:22:52 +0200
commit1bf7a18fec76cf46a5b8710a75371e23b68d147d (patch)
treeea445edda6c4bc0fa670effce4ef1b0eaf906258 /passes/hierarchy
parent746aac540b815099c6a63077010555369d7fdd5a (diff)
Added module->ports
Diffstat (limited to 'passes/hierarchy')
-rw-r--r--passes/hierarchy/hierarchy.cc2
-rw-r--r--passes/hierarchy/submod.cc7
2 files changed, 5 insertions, 4 deletions
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index 50b4989d..2f28afb2 100644
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -126,6 +126,8 @@ static void generate(RTLIL::Design *design, const std::vector<std::string> &cell
wire->port_output = decl.output;
}
+ mod->fixup_ports();
+
for (auto &para : parameters)
log(" ignoring parameter %s.\n", RTLIL::id2cstr(para));
diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc
index 89f45e02..1b03ab55 100644
--- a/passes/hierarchy/submod.cc
+++ b/passes/hierarchy/submod.cc
@@ -106,7 +106,7 @@ struct SubmodWorker
RTLIL::Module *new_mod = new RTLIL::Module;
new_mod->name = submod.full_name;
design->add(new_mod);
- int port_counter = 1, auto_name_counter = 1;
+ int auto_name_counter = 1;
std::set<RTLIL::IdString> all_wire_names;
for (auto &it : wire_flags) {
@@ -151,9 +151,6 @@ struct SubmodWorker
new_wire->start_offset = wire->start_offset;
new_wire->attributes = wire->attributes;
- if (new_wire->port_input || new_wire->port_output)
- new_wire->port_id = port_counter++;
-
if (new_wire->port_input && new_wire->port_output)
log(" signal %s: inout %s\n", wire->name.c_str(), new_wire->name.c_str());
else if (new_wire->port_input)
@@ -166,6 +163,8 @@ struct SubmodWorker
flags.new_wire = new_wire;
}
+ new_mod->fixup_ports();
+
for (RTLIL::Cell *cell : submod.cells) {
RTLIL::Cell *new_cell = new_mod->addCell(cell->name, cell);
for (auto &conn : new_cell->connections_)