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authorClifford Wolf <clifford@clifford.at>2013-03-26 19:11:53 +0100
committerClifford Wolf <clifford@clifford.at>2013-03-26 19:11:53 +0100
commit6a231816fa87f767eda2837faea838a57722e481 (patch)
tree5e3477ed488b4ee8e280869a584bb0fdb8d60231 /passes/hierarchy
parent26f2439551697c0511bd0c5375ce69e26973d4ca (diff)
Collect parameters in hierarchy -generate (and do nothing with them)
Diffstat (limited to 'passes/hierarchy')
-rw-r--r--passes/hierarchy/hierarchy.cc9
1 files changed, 8 insertions, 1 deletions
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index 04274990..8ef169ce 100644
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -50,17 +50,21 @@ static void generate(RTLIL::Design *design, const std::vector<std::string> &cell
for (auto &celltype : found_celltypes)
{
std::set<std::string> portnames;
+ std::set<std::string> parameters;
std::map<std::string, int> portwidths;
log("Generate module for cell type %s:\n", celltype.c_str());
for (auto i1 : design->modules)
for (auto i2 : i1.second->cells)
- if (i2.second->type == celltype)
+ if (i2.second->type == celltype) {
for (auto &conn : i2.second->connections) {
if (conn.first[0] != '$')
portnames.insert(conn.first);
portwidths[conn.first] = std::max(portwidths[conn.first], conn.second.width);
}
+ for (auto &para : i2.second->parameters)
+ parameters.insert(para.first);
+ }
for (auto &decl : portdecls)
if (decl.index > 0)
@@ -121,6 +125,9 @@ static void generate(RTLIL::Design *design, const std::vector<std::string> &cell
mod->add(wire);
}
+ for (auto &para : parameters)
+ log(" ignoring parameter %s.\n", RTLIL::id2cstr(para));
+
log(" module %s created.\n", RTLIL::id2cstr(mod->name));
}
}