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authorClifford Wolf <clifford@clifford.at>2014-06-07 12:17:06 +0200
committerClifford Wolf <clifford@clifford.at>2014-06-07 12:17:11 +0200
commit744e51846776a304828301914f5cd74fb7d0a5ca (patch)
treebc179215fe01bd0a44311ace29e71fdc12bf87b9 /passes/hierarchy
parente275e8eef9ae47670075bd73a671f3acd3c0ca52 (diff)
fixed cell array handling of positional arguments
Diffstat (limited to 'passes/hierarchy')
-rw-r--r--passes/hierarchy/hierarchy.cc13
1 files changed, 11 insertions, 2 deletions
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index 6890cb9e..d8a23c72 100644
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -221,9 +221,18 @@ static bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool fla
for (auto &conn : cell->connections) {
int conn_size = conn.second.width;
- if (mod->wires.count(conn.first) == 0)
+ std::string portname = conn.first;
+ if (portname.substr(0, 1) == "$") {
+ int port_id = atoi(portname.substr(1).c_str());
+ for (auto &wire_it : mod->wires)
+ if (wire_it.second->port_id == port_id) {
+ portname = wire_it.first;
+ break;
+ }
+ }
+ if (mod->wires.count(portname) == 0)
log_error("Array cell `%s.%s' connects to unkown port `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(conn.first));
- int port_size = mod->wires.at(conn.first)->width;
+ int port_size = mod->wires.at(portname)->width;
if (conn_size == port_size)
continue;
if (conn_size != port_size*num)