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authorClifford Wolf <clifford@clifford.at>2014-07-28 11:08:55 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-28 11:27:48 +0200
commit7bd2d1064f2eceddc3c93c121c4154a2f594a040 (patch)
tree563de1df5e323d0f217a51e29acb56c9e9f1327d /passes/hierarchy
parentd86a25f145012ccb6b2048af3aae22f13b97b505 (diff)
Using log_assert() instead of assert()
Diffstat (limited to 'passes/hierarchy')
-rw-r--r--passes/hierarchy/hierarchy.cc4
-rw-r--r--passes/hierarchy/submod.cc2
2 files changed, 3 insertions, 3 deletions
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index 8aec25eb..c869ec72 100644
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -98,7 +98,7 @@ static void generate(RTLIL::Design *design, const std::vector<std::string> &cell
generate_port_decl_t d = decl;
d.portname = portname;
d.index = *indices.begin();
- assert(!indices.empty());
+ log_assert(!indices.empty());
indices.erase(d.index);
ports[d.index-1] = d;
portwidths[d.portname] = std::max(portwidths[d.portname], 1);
@@ -110,7 +110,7 @@ static void generate(RTLIL::Design *design, const std::vector<std::string> &cell
portnames.erase(portname);
}
- assert(indices.empty());
+ log_assert(indices.empty());
RTLIL::Module *mod = new RTLIL::Module;
mod->name = celltype;
diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc
index d32b5e1d..84c6b916 100644
--- a/passes/hierarchy/submod.cc
+++ b/passes/hierarchy/submod.cc
@@ -171,7 +171,7 @@ struct SubmodWorker
for (auto &conn : new_cell->connections_)
for (auto &bit : conn.second)
if (bit.wire != NULL) {
- assert(wire_flags.count(bit.wire) > 0);
+ log_assert(wire_flags.count(bit.wire) > 0);
bit.wire = wire_flags[bit.wire].new_wire;
}
log(" cell %s (%s)\n", new_cell->name.c_str(), new_cell->type.c_str());