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authorClifford Wolf <clifford@clifford.at>2014-08-02 13:11:01 +0200
committerClifford Wolf <clifford@clifford.at>2014-08-02 13:19:57 +0200
commitb9bd22b8c8d46284fba4d4c1cbd09092a9ccc5c3 (patch)
treefa56668843c23b8d03a0652be802410f888c6384 /passes/hierarchy
parent14412e6c957a34381c33740426b35f7b90a446be (diff)
More cleanups related to RTLIL::IdString usage
Diffstat (limited to 'passes/hierarchy')
-rw-r--r--passes/hierarchy/hierarchy.cc30
-rw-r--r--passes/hierarchy/submod.cc10
2 files changed, 20 insertions, 20 deletions
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index 67b57a94..28b4ad99 100644
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -35,7 +35,7 @@ namespace {
static void generate(RTLIL::Design *design, const std::vector<std::string> &celltypes, const std::vector<generate_port_decl_t> &portdecls)
{
- std::set<std::string> found_celltypes;
+ std::set<RTLIL::IdString> found_celltypes;
for (auto i1 : design->modules_)
for (auto i2 : i1.second->cells_)
@@ -52,9 +52,9 @@ static void generate(RTLIL::Design *design, const std::vector<std::string> &cell
for (auto &celltype : found_celltypes)
{
- std::set<std::string> portnames;
- std::set<std::string> parameters;
- std::map<std::string, int> portwidths;
+ std::set<RTLIL::IdString> portnames;
+ std::set<RTLIL::IdString> parameters;
+ std::map<RTLIL::IdString, int> portwidths;
log("Generate module for cell type %s:\n", celltype.c_str());
for (auto i1 : design->modules_)
@@ -94,7 +94,7 @@ static void generate(RTLIL::Design *design, const std::vector<std::string> &cell
}
while (portnames.size() > 0) {
- std::string portname = *portnames.begin();
+ RTLIL::IdString portname = *portnames.begin();
for (auto &decl : portdecls)
if (decl.index == 0 && !fnmatch(decl.portname.c_str(), RTLIL::unescape_id(portname).c_str(), FNM_NOESCAPE)) {
generate_port_decl_t d = decl;
@@ -144,20 +144,20 @@ static bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool fla
RTLIL::Cell *cell = cell_it.second;
if (cell->type.substr(0, 7) == "$array:") {
- int pos_idx = cell->type.find_first_of(':');
- int pos_num = cell->type.find_first_of(':', pos_idx + 1);
- int pos_type = cell->type.find_first_of(':', pos_num + 1);
- int idx = atoi(cell->type.substr(pos_idx + 1, pos_num).c_str());
- int num = atoi(cell->type.substr(pos_num + 1, pos_type).c_str());
+ int pos_idx = cell->type.str().find_first_of(':');
+ int pos_num = cell->type.str().find_first_of(':', pos_idx + 1);
+ int pos_type = cell->type.str().find_first_of(':', pos_num + 1);
+ int idx = atoi(cell->type.str().substr(pos_idx + 1, pos_num).c_str());
+ int num = atoi(cell->type.str().substr(pos_num + 1, pos_type).c_str());
array_cells[cell] = std::pair<int, int>(idx, num);
- cell->type = cell->type.substr(pos_type + 1);
+ cell->type = cell->type.str().substr(pos_type + 1);
}
if (design->modules_.count(cell->type) == 0)
{
- if (design->modules_.count("$abstract" + cell->type))
+ if (design->modules_.count("$abstract" + cell->type.str()))
{
- cell->type = design->modules_.at("$abstract" + cell->type)->derive(design, cell->parameters);
+ cell->type = design->modules_.at("$abstract" + cell->type.str())->derive(design, cell->parameters);
cell->parameters.clear();
did_something = true;
continue;
@@ -220,7 +220,7 @@ static bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool fla
for (auto &conn : cell->connections_) {
int conn_size = conn.second.size();
- std::string portname = conn.first;
+ RTLIL::IdString portname = conn.first;
if (portname.substr(0, 1) == "$") {
int port_id = atoi(portname.substr(1).c_str());
for (auto &wire_it : mod->wires_)
@@ -447,7 +447,7 @@ struct HierarchyPass : public Pass {
bool did_something_once = false;
while (did_something) {
did_something = false;
- std::vector<std::string> modnames;
+ std::vector<RTLIL::IdString> modnames;
modnames.reserve(design->modules_.size());
for (auto &mod_it : design->modules_)
modnames.push_back(mod_it.first);
diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc
index 2a47002e..89f45e02 100644
--- a/passes/hierarchy/submod.cc
+++ b/passes/hierarchy/submod.cc
@@ -108,7 +108,7 @@ struct SubmodWorker
design->add(new_mod);
int port_counter = 1, auto_name_counter = 1;
- std::set<std::string> all_wire_names;
+ std::set<RTLIL::IdString> all_wire_names;
for (auto &it : wire_flags) {
all_wire_names.insert(it.first->name);
}
@@ -134,7 +134,7 @@ struct SubmodWorker
if (flags.is_int_driven && flags.is_ext_driven)
new_wire_port_input = true, new_wire_port_output = true;
- std::string new_wire_name = wire->name;
+ std::string new_wire_name = wire->name.str();
if (new_wire_port_input || new_wire_port_output) {
while (new_wire_name[0] == '$') {
std::string next_wire_name = stringf("\\n%d", auto_name_counter++);
@@ -228,7 +228,7 @@ struct SubmodWorker
if (submodules.count(submod_str) == 0) {
submodules[submod_str].name = submod_str;
- submodules[submod_str].full_name = module->name + "_" + submod_str;
+ submodules[submod_str].full_name = module->name.str() + "_" + submod_str;
while (design->modules_.count(submodules[submod_str].full_name) != 0 ||
module->count_id(submodules[submod_str].full_name) != 0)
submodules[submod_str].full_name += "_";
@@ -306,12 +306,12 @@ struct SubmodPass : public Pass {
Pass::call(design, "opt_clean");
log_header("Continuing SUBMOD pass.\n");
- std::set<std::string> handled_modules;
+ std::set<RTLIL::IdString> handled_modules;
bool did_something = true;
while (did_something) {
did_something = false;
- std::vector<std::string> queued_modules;
+ std::vector<RTLIL::IdString> queued_modules;
for (auto &mod_it : design->modules_)
if (handled_modules.count(mod_it.first) == 0 && design->selected_whole_module(mod_it.first))
queued_modules.push_back(mod_it.first);