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| author | Ruben Undheim <ruben.undheim@gmail.com> | 2016-09-23 07:11:40 +0200 |
|---|---|---|
| committer | Ruben Undheim <ruben.undheim@gmail.com> | 2016-09-23 07:11:40 +0200 |
| commit | 5e5a84772ea91c96abc74d5d456ca7bf26127c4a (patch) | |
| tree | 7d3b054da867cfce96dfb4fdc61feb8e917a4b46 /passes/memory/memory_bram.cc | |
| parent | 324696a07a1a9822022362ed79875a9f1fee124c (diff) | |
| parent | 4f096fe65b77435daba019248273e547fa18d167 (diff) | |
Merge tag 'upstream/0.6+20160920git0c697b9'
Diffstat (limited to 'passes/memory/memory_bram.cc')
| -rw-r--r-- | passes/memory/memory_bram.cc | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/passes/memory/memory_bram.cc b/passes/memory/memory_bram.cc index f2d9b584..a7f9cf38 100644 --- a/passes/memory/memory_bram.cc +++ b/passes/memory/memory_bram.cc @@ -656,6 +656,9 @@ grow_read_ports:; bool transp = rd_transp[cell_port_i] == State::S1; SigBit clksig = rd_clk[cell_port_i]; + if (wr_ports == 0) + transp = false; + pair<SigBit, bool> clkdom(clksig, clkpol); if (!clken) clkdom = pair<SigBit, bool>(State::S1, false); @@ -826,7 +829,7 @@ grow_read_ports:; State padding = State::Sx; for (int j = 0; j < bram.dbits; j++) if (init_offset+i < GetSize(initdata) && init_shift+j < GetSize(initdata[init_offset+i])) - padding = initparam[i*bram.dbits+j] = initdata[init_offset+i][init_shift+j]; + initparam[i*bram.dbits+j] = initdata[init_offset+i][init_shift+j]; else initparam[i*bram.dbits+j] = padding; } @@ -1211,7 +1214,7 @@ struct MemoryBramPass : public Pass { { rules_t rules; - log_header("Executing MEMORY_BRAM pass (mapping $mem cells to block memories).\n"); + log_header(design, "Executing MEMORY_BRAM pass (mapping $mem cells to block memories).\n"); size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { |