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authorClifford Wolf <clifford@clifford.at>2014-07-28 11:08:55 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-28 11:27:48 +0200
commit7bd2d1064f2eceddc3c93c121c4154a2f594a040 (patch)
tree563de1df5e323d0f217a51e29acb56c9e9f1327d /passes/memory/memory_collect.cc
parentd86a25f145012ccb6b2048af3aae22f13b97b505 (diff)
Using log_assert() instead of assert()
Diffstat (limited to 'passes/memory/memory_collect.cc')
-rw-r--r--passes/memory/memory_collect.cc23
1 files changed, 11 insertions, 12 deletions
diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc
index d2803ae7..40c68abc 100644
--- a/passes/memory/memory_collect.cc
+++ b/passes/memory/memory_collect.cc
@@ -22,7 +22,6 @@
#include <sstream>
#include <algorithm>
#include <stdlib.h>
-#include <assert.h>
static bool memcells_cmp(RTLIL::Cell *a, RTLIL::Cell *b)
{
@@ -136,12 +135,12 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
mem->parameters["\\SIZE"] = RTLIL::Const(memory->size);
mem->parameters["\\ABITS"] = RTLIL::Const(addr_bits);
- assert(sig_wr_clk.size() == wr_ports);
- assert(sig_wr_clk_enable.size() == wr_ports && sig_wr_clk_enable.is_fully_const());
- assert(sig_wr_clk_polarity.size() == wr_ports && sig_wr_clk_polarity.is_fully_const());
- assert(sig_wr_addr.size() == wr_ports * addr_bits);
- assert(sig_wr_data.size() == wr_ports * memory->width);
- assert(sig_wr_en.size() == wr_ports * memory->width);
+ log_assert(sig_wr_clk.size() == wr_ports);
+ log_assert(sig_wr_clk_enable.size() == wr_ports && sig_wr_clk_enable.is_fully_const());
+ log_assert(sig_wr_clk_polarity.size() == wr_ports && sig_wr_clk_polarity.is_fully_const());
+ log_assert(sig_wr_addr.size() == wr_ports * addr_bits);
+ log_assert(sig_wr_data.size() == wr_ports * memory->width);
+ log_assert(sig_wr_en.size() == wr_ports * memory->width);
mem->parameters["\\WR_PORTS"] = RTLIL::Const(wr_ports);
mem->parameters["\\WR_CLK_ENABLE"] = wr_ports ? sig_wr_clk_enable.as_const() : RTLIL::Const(0, 0);
@@ -152,11 +151,11 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
mem->set("\\WR_DATA", sig_wr_data);
mem->set("\\WR_EN", sig_wr_en);
- assert(sig_rd_clk.size() == rd_ports);
- assert(sig_rd_clk_enable.size() == rd_ports && sig_rd_clk_enable.is_fully_const());
- assert(sig_rd_clk_polarity.size() == rd_ports && sig_rd_clk_polarity.is_fully_const());
- assert(sig_rd_addr.size() == rd_ports * addr_bits);
- assert(sig_rd_data.size() == rd_ports * memory->width);
+ log_assert(sig_rd_clk.size() == rd_ports);
+ log_assert(sig_rd_clk_enable.size() == rd_ports && sig_rd_clk_enable.is_fully_const());
+ log_assert(sig_rd_clk_polarity.size() == rd_ports && sig_rd_clk_polarity.is_fully_const());
+ log_assert(sig_rd_addr.size() == rd_ports * addr_bits);
+ log_assert(sig_rd_data.size() == rd_ports * memory->width);
mem->parameters["\\RD_PORTS"] = RTLIL::Const(rd_ports);
mem->parameters["\\RD_CLK_ENABLE"] = rd_ports ? sig_rd_clk_enable.as_const() : RTLIL::Const(0, 0);