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authorClifford Wolf <clifford@clifford.at>2014-07-22 19:56:17 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-22 20:39:37 +0200
commita233762a815fc180b371f699e865a7d7aed77bca (patch)
tree722e54921bbc09595c046c6045cd531445945fc9 /passes/memory/memory_collect.cc
parent3b5f4ff39c94a5a664043f35b95a50240ffe9d12 (diff)
SigSpec refactoring: renamed chunks and width to __chunks and __width
Diffstat (limited to 'passes/memory/memory_collect.cc')
-rw-r--r--passes/memory/memory_collect.cc32
1 files changed, 16 insertions, 16 deletions
diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc
index 028841f6..6c9e1b77 100644
--- a/passes/memory/memory_collect.cc
+++ b/passes/memory/memory_collect.cc
@@ -142,16 +142,16 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
sig_wr_clk_enable.optimize();
sig_wr_clk_polarity.optimize();
- assert(sig_wr_clk.width == wr_ports);
- assert(sig_wr_clk_enable.width == wr_ports && sig_wr_clk_enable.is_fully_const());
- assert(sig_wr_clk_polarity.width == wr_ports && sig_wr_clk_polarity.is_fully_const());
- assert(sig_wr_addr.width == wr_ports * addr_bits);
- assert(sig_wr_data.width == wr_ports * memory->width);
- assert(sig_wr_en.width == wr_ports * memory->width);
+ assert(sig_wr_clk.__width == wr_ports);
+ assert(sig_wr_clk_enable.__width == wr_ports && sig_wr_clk_enable.is_fully_const());
+ assert(sig_wr_clk_polarity.__width == wr_ports && sig_wr_clk_polarity.is_fully_const());
+ assert(sig_wr_addr.__width == wr_ports * addr_bits);
+ assert(sig_wr_data.__width == wr_ports * memory->width);
+ assert(sig_wr_en.__width == wr_ports * memory->width);
mem->parameters["\\WR_PORTS"] = RTLIL::Const(wr_ports);
- mem->parameters["\\WR_CLK_ENABLE"] = wr_ports ? sig_wr_clk_enable.chunks[0].data : RTLIL::Const(0, 0);
- mem->parameters["\\WR_CLK_POLARITY"] = wr_ports ? sig_wr_clk_polarity.chunks[0].data : RTLIL::Const(0, 0);
+ mem->parameters["\\WR_CLK_ENABLE"] = wr_ports ? sig_wr_clk_enable.__chunks[0].data : RTLIL::Const(0, 0);
+ mem->parameters["\\WR_CLK_POLARITY"] = wr_ports ? sig_wr_clk_polarity.__chunks[0].data : RTLIL::Const(0, 0);
mem->connections["\\WR_CLK"] = sig_wr_clk;
mem->connections["\\WR_ADDR"] = sig_wr_addr;
@@ -162,16 +162,16 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
sig_rd_clk_polarity.optimize();
sig_rd_transparent.optimize();
- assert(sig_rd_clk.width == rd_ports);
- assert(sig_rd_clk_enable.width == rd_ports && sig_rd_clk_enable.is_fully_const());
- assert(sig_rd_clk_polarity.width == rd_ports && sig_rd_clk_polarity.is_fully_const());
- assert(sig_rd_addr.width == rd_ports * addr_bits);
- assert(sig_rd_data.width == rd_ports * memory->width);
+ assert(sig_rd_clk.__width == rd_ports);
+ assert(sig_rd_clk_enable.__width == rd_ports && sig_rd_clk_enable.is_fully_const());
+ assert(sig_rd_clk_polarity.__width == rd_ports && sig_rd_clk_polarity.is_fully_const());
+ assert(sig_rd_addr.__width == rd_ports * addr_bits);
+ assert(sig_rd_data.__width == rd_ports * memory->width);
mem->parameters["\\RD_PORTS"] = RTLIL::Const(rd_ports);
- mem->parameters["\\RD_CLK_ENABLE"] = rd_ports ? sig_rd_clk_enable.chunks[0].data : RTLIL::Const(0, 0);
- mem->parameters["\\RD_CLK_POLARITY"] = rd_ports ? sig_rd_clk_polarity.chunks[0].data : RTLIL::Const(0, 0);
- mem->parameters["\\RD_TRANSPARENT"] = rd_ports ? sig_rd_transparent.chunks[0].data : RTLIL::Const(0, 0);
+ mem->parameters["\\RD_CLK_ENABLE"] = rd_ports ? sig_rd_clk_enable.__chunks[0].data : RTLIL::Const(0, 0);
+ mem->parameters["\\RD_CLK_POLARITY"] = rd_ports ? sig_rd_clk_polarity.__chunks[0].data : RTLIL::Const(0, 0);
+ mem->parameters["\\RD_TRANSPARENT"] = rd_ports ? sig_rd_transparent.__chunks[0].data : RTLIL::Const(0, 0);
mem->connections["\\RD_CLK"] = sig_rd_clk;
mem->connections["\\RD_ADDR"] = sig_rd_addr;