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| author | Ruben Undheim <ruben.undheim@gmail.com> | 2019-03-28 23:35:03 +0100 |
|---|---|---|
| committer | Ruben Undheim <ruben.undheim@gmail.com> | 2019-03-28 23:35:03 +0100 |
| commit | ff5734b20220e6fb4a3913cf5279ed94bb5156ea (patch) | |
| tree | 4c438282926d7bac304ad3ad6ad89523c4c1d784 /passes/memory/memory_collect.cc | |
| parent | db3c67fd6e140893450a44870ee9a75dd1f48b27 (diff) | |
Imported GIT HEAD: 0.8+20190328git32bd0f2
Diffstat (limited to 'passes/memory/memory_collect.cc')
| -rw-r--r-- | passes/memory/memory_collect.cc | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc index 70d98713..369fcc84 100644 --- a/passes/memory/memory_collect.cc +++ b/passes/memory/memory_collect.cc @@ -184,9 +184,6 @@ Cell *handle_memory(Module *module, RTLIL::Memory *memory) mem->parameters["\\OFFSET"] = Const(memory->start_offset); mem->parameters["\\SIZE"] = Const(memory->size); mem->parameters["\\ABITS"] = Const(addr_bits); - - while (GetSize(init_data) > 1 && init_data.bits.back() == State::Sx && init_data.bits[GetSize(init_data)-2] == State::Sx) - init_data.bits.pop_back(); mem->parameters["\\INIT"] = init_data; log_assert(sig_wr_clk.size() == wr_ports); |