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authorClifford Wolf <clifford@clifford.at>2014-07-27 01:49:51 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-27 01:49:51 +0200
commitf9946232adf887e5aa4a48c64f88eaa17e424009 (patch)
tree39594b3287c3369752668456c4a6b1735fb66e77 /passes/memory/memory_map.cc
parentd7916a49aff3c47b7c1ce07abe3b6e3d5714079b (diff)
Refactoring: Renamed RTLIL::Module::wires to wires_
Diffstat (limited to 'passes/memory/memory_map.cc')
-rw-r--r--passes/memory/memory_map.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc
index 32c7e63a..4f166653 100644
--- a/passes/memory/memory_map.cc
+++ b/passes/memory/memory_map.cc
@@ -131,7 +131,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
c->set("\\D", data_reg_in.back());
std::string w_out_name = stringf("%s[%d]", cell->parameters["\\MEMID"].decode_string().c_str(), i);
- if (module->wires.count(w_out_name) > 0)
+ if (module->wires_.count(w_out_name) > 0)
w_out_name = genid(cell->name, "", i, "$q");
RTLIL::Wire *w_out = module->addWire(w_out_name, mem_width);